Methods for precise definition of integrated circuit chip edges

• US 5,691,248 A
• Filed: 07/26/1995
• Issued: 11/25/1997
• Est. Priority Date: 07/26/1995
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Cronin, John Edward, Pierson, Bernadette Ann, Howell, Wayne John, Schmidt, Dennis Arthur, Kalter, Howard Leo, Palagonia, Anthony, Marmillion, Patricia Ellen
• Primary Examiner(s): Breneman, R. Bruce
• Assistant Examiner(s): ALANKO, ANITA KAREN
• Application Number:
  US08/507,186
• Time in Patent Office: 853 Days
• Field of Search: 156/636.1, 156/645.1, 437/226, 437/227, 148/DIG. 28
• US Class Current: 438/109
• CPC Class Codes: H01L 21/78 with subsequent division of the substrate into plural individual devices cutting to change the surface-physical characteristics or shape of semiconductor bodies H01L21/304
• CPC Class Codes: H01L 2224/24145 the bodies being stacked
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/10253 Silicon [Si]
• CPC Class Codes: Y10S 148/028 Dicing
• CPC Class Codes: Y10S 438/977 Thinning or removal of substrate

Abstract

Integrated Circuit ("IC") chips are formed with precisely defined edges and sizing. At the wafer processing level, trenches are lithographically etched in the kerf regions to define the edges of the IC chips on the wafer. The trenches are filled with insulating material, and upper level wiring and metallization is completed for the IC chips on the wafer. Further trenches are defined down to the filled previously formed trenches. The wafer is thinned from its bottom up to the filled trenches, and the insulating material therein is removed to separate the individual IC chips from the wafer. The precision of IC chip edge definition facilitates forming the IC chips into stacks more easily because many stack level alignment processes become unnecessary.

Claims

1. A method for use in defining at least one edge of an integrated circuit ("IC") chip, said IC chip comprising part of a wafer having a first planar main surface and a second planar main surface, a portion of said second planar main surface of said wafer being parallel to a planar main surface of said IC chip, said method comprising the steps of:

(a) lithographically creating a first trench in said wafer that intersects said first planar main surface of said wafer, said first trench having a bottom;

(b) filling said first trench with an insulating material;

(c) forming a transfer metal layer above said first planar main surface of said wafer, said transfer metal layer being mechanically and electrically coupled to said IC chip, said transfer metal layer extending over said trench;

(d) forming a second trench through said transfer metal layer and coincident with said first trench; and

(e) polishing said planar main surface of said IC chip toward said bottom of said first trench and toward said first planar main surface of said wafer to thin said IC chip such that said first trench and said second trench define the at least one edge of the IC chip and such that an end of a transfer metal lead of the transfer metal layer is aligned with the at least one edge of the IC chip.

2. The method of claim 1, wherein said step of filling said first trench comprises filling said first trench with a mechanically rigid insulating material for providing mechanical stability of said IC chip relative to said wafer during said polishing step (c).

3. The method of claim 1, further comprising mechanically dicing said wafer along a path within said first trench and collinear therewith such that said IC chip is separated from said wafer.

4. The method of claim 3, further comprising removing a kerf comprising said insulating material following said mechanical dicing to expose the at least one edge of the IC chip.

5. The method of claim 1, further in combination with repeating said method in the formation of a plurality of IC chips, each having said at least one edge, and stacking said plurality of IC chips such that the at least one edge of each IC chip is commonly aligned to form a side surface of a stack of said plurality of IC chips.

6. A method for use in defining at least one edge of an integrated circuit ("IC") chip, said IC chip comprising part of a wafer having a first planar main surface and a second planar main surface, a portion of said second planar main surface of said wafer being parallel to a planar main surface of said IC chip, said method comprising the steps of:

(a) lithographically creating a first trench in said wafer that intersects said first planar main surface of said wafer;

(b) forming two insulating layers within the first trench, a first insulating layer of said two insulating layers having a surface comprising the at least one edge of said IC chip, a second insulating layer of the two insulating layers comprising a removable kerf region;

(c) forming a transfer metal layer above said first planar main surface of said wafer, said transfer metal layer being mechanically and electrically coupled to said IC chip, said transfer metal layer extending over said trench;

(d) forming a second trench through said transfer metal layer and coincident with said surface of said first insulating layer comprising the at least one edge of the IC chip such that the at least one edge of the IC chip is further defined and such that an end of a transfer metal lead of said transfer metal layer is aligned with the at least one edge of the IC chip; and

(e) thinning said IC chip from said planar main surface thereof and toward said first planar main surface of said wafer to facilitate separation of said IC chip from said wafer and removal of said removable kerf region to define the at least one edge of the IC chip.

7. The method of claim 6, wherein said forming step (b) comprises forming said first insulating layer as a conformal insulating layer on at least one sidewall of said first trench such that remaining space exists in said first trench.

8. The method of claim 7, wherein said forming step (b) comprises employing a thermal oxidation process to form said first insulating layer as a conformal oxide layer.

9. The method of claim 7, wherein said forming step (b) comprises forming the first insulating layer to have a lip extending out of said first trench and onto said first planar main surface of said wafer.

10. The method or claim 7, wherein said forming step (b) comprises forming said second insulating layer by said filling remaining space inside said first trench with a second insulating material.

11. The method of claim 10, wherein said forming step (b) comprises filling said remaining space inside said first trench with one of a polyimide or an epoxy.

12. The method of claim 6, further comprising removing said second insulating layer to separate the IC chip from the wafer and to define the at least one edge of the IC chip.

13. The method of claim 12, wherein said removing said second insulating layer comprises a performing a chemical removal process.

14. The method of claim 12, wherein said removing said second insulating layer comprises mechanically dicing through said second insulating layer followed by chemically removing remaining second insulating layer on the at least one edge of the IC chip.

15. The method of claim 6, further in combination with repeating said method in the formation of a plurality of IC chips, each having said at least one edge, and stacking said plurality of IC chips such that the at least one edge of each IC chip is commonly aligned to form a side surface of a stack of said plurality of IC chips.

16. A method for defining at least one edge of an integrated circuit ("IC") chip, said IC chip comprising part of a wafer having a first planar main surface and a second planar main surface, a portion of said second planar main surface of said wafer being parallel to a planar main surface of said IC chip, said method comprising the steps of:

(a) lithographically creating a first trench in said wafer that intersects said first planar main surface of said wafer, said first trench defining the at least one edge of said IC chip;

(b) forming an insulating layer within said first trench;

(c) forming a transfer metal layer above said first planar main surface of said wafer, said transfer metal layer being mechanically and electrically coupled to said IC chip, said transfer metal layer extending over said trench;

(d) forming a second trench through said transfer metal layer and coincident with said outer sidewalls of said pair of first trenches such that the at least one edge of the IC chip is further defined and such that ends of transfer metal leads of said transfer metal layer are aligned with the at least one edge of the IC chip;

(e) dicing said wafer along a path substantially parallel to said first trench and outside of said IC chip to form a kerf region between said first trench and said path; and

(f) removing said kerf region and said insulating layer to form the at least one edge of said IC chip.

17. The method of claim 16, further comprising thinning said wafer toward a bottom of said first trench and toward said first planar main surface of said wafer to facilitate said removing step (f).

18. The method of claim 16, wherein said creating step (a) comprises lithographically creating a pair of first trenches, one trench of the pair of first trenches defining the at least one edge of the IC chip, another trench of the pair of first trenches defining at least one edge of another, adjacent IC chip of the wafer.

19. The method of claim 18, wherein said dicing step (e) comprises dicing said wafer along a path between said pair of first trenches.

20. The method of claim 16, wherein said pair of first trenches together comprise a pair of outer sidewalls.

21. The method of claim 16, further in combination with repeating said method in the formation of a plurality of IC chips, each having said at least one edge, and stacking said plurality of IC chips such that the at least one edge of each IC chip is commonly aligned to form a side surface of a stack of said plurality of IC chips.

22. The method of claim 16, wherein said removing step (f) is performed using chemical dipping.

23. The method of claim 16, wherein said forming step (b) comprises forming an oxide insulating layer in the first trench by employing thermal oxidation.