Programmable analog array and method for establishing a feedback loop therein

• US 5,691,664 A
• Filed: 01/16/1996
• Issued: 11/25/1997
• Est. Priority Date: 01/16/1996
• Status: Expired due to Term

• Current Assignee: Neadiwa Software Kr LLC (Intellectual Ventures LLC)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Anderson, David J., Bersch, Danny A.
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): LAM, TUAN THIEU
• Application Number:
  US08/586,503
• Time in Patent Office: 679 Days
• Field of Search: 327/564-566, 326/38, 326/39, 326/41, 326/47
• US Class Current: 327/565
• CPC Class Codes: H03K 19/177 arranged in matrix form
• CPC Class Codes: H03K 19/17704 the logic functions being realised by the interconnection of rows and columns

Abstract

A programmable analog array (10) comprises an array of configurable cells (11), each cell (11) including analog circuitry (12) and digital circuitry (14). The cells (11) are configured for a particular functional application. The digital circuitry (14) converts an analog signal generated by the analog circuitry (12) into digital control information, which is then used to adjust the analog circuitry (12). Therefore, the analog circuitry (12) and the digital circuitry (14) form a digital feedback loop. The digital feedback loop is established either within a single cell or among neighboring cells. Thus, the digital feedback loop is established without using a global data bus.

Claims

1. A programmable analog array, comprising:

an array of cells, a plurality of cells in the array of cells including analog circuitry which is configurable as a plurality of circuit functions and digital circuitry which converts an analog signal received from the analog circuitry into digital information;

a local feedback loop established within the array of cells the local feedback loop reconfiguring the analog circuitry in accordance with the digital information;

interconnection circuitry coupled to the array of cells, wherein the interconnection circuitry enables interconnection of different cells in the array of cells; and

an accessing circuit, wherein the accessing circuit selectively accesses a first cell of the plurality of cells, transmits cell configuration data to the first cell to internally configure the first cell as one of the plurality of circuit functions, and transmits interconnection data to the interconnection circuitry.

2. The programable analog array of claim 1, wherein the local feedback loop is established between the first cell and a second cell of the plurality of cells, the first cell and the second cell being coupled to each other via the interconnection circuitry.

3. The programmable analog array of claim 1, wherein the local feedback loop is established within the first cell.

4. The programable analog array of claim 1, wherein the first cell further includes a memory unit for storing the cell configuration data of the first cell.

5. The programmable analog array of claim 1, wherein the first cell further includes switch circuitry, and wherein the switch circuitry configures the analog circuitry of the first cell in accordance with the cell configuration data.

6. The programable analog array of claim 1, wherein the accessing circuit includes a data storage element for storing the cell configuration data and for storing the interconnection data.

7. The programmable analog array of claim 1, wherein the first cell includes switch circuitry, and wherein the switch circuitry configures the digital circuitry of the first cell in accordance with the cell configuration data.

8. The programmable analog array of claim 1, wherein analog circuitry of the first cell includes:

an operational amplifier; and

an analog circuit element coupled to the operational amplifier, the analog circuit element having internal components, wherein the internal components have component values and are interconnected.

9. The programmable analog array of claim 1, wherein the first cell and a second cell of the plurality of cells are configured to produce an automatic gain control circuit, and wherein the automatic gain control circuit includes:

an amplifier configured from analog circuitry of the first cell, wherein the amplifier has an input coupled for receiving an input signal, a control input, and an output;

a peak detector configured from analog circuitry of the second cell, wherein the peak detector has an input coupled to the output of the amplifier, and an output;

a comparator configured from the analog circuitry of the first cell, wherein the comparator has an inverting input coupled to the output of the peak detector, a non-inverting input coupled for receiving a reference voltage, a first output and a second output; and

a counter configured from digital circuitry of the first cell, wherein the counter has a clock input coupled for receiving a clock signal, a first control input coupled to the first output of the comparator, a second control input coupled to the second output of the comparator, and an output coupled to the control input of the amplifier.

10. The programmable analog array of claim 1, wherein the first cell and a second cell of the plurality of cells are configured to produce a phase locked loop, and wherein the phase locked loop includes:

an oscillator configured from analog circuitry of the first cell, wherein the oscillator has an input and an output;

a first counter configured from digital circuitry of the second cell, wherein the first counter has a clock input coupled to the output of the oscillator, a control input coupled for receiving a first voltage, and an output;

a multiplexer configured from the digital circuitry of the second cell, wherein the multiplexer has an input coupled to the output of the first counter, and an output;

a logic gate configured from the digital circuitry of the second cell, wherein the logic gate has a first input coupled to the output of the multiplexer, a second input coupled for receiving an input signal, and an output;

a filter configured from analog circuitry of the second cell, wherein the filter has an input coupled to the output of the logic gate, and an output;

a comparator configured from the analog circuitry of the first cell, wherein the comparator has a non-inverting input coupled to the output of the filter, an inverting input coupled for receiving a reference voltage, a first output, and a second output; and

a second counter configured from digital circuitry of the first cell, wherein the second counter has a clock input coupled for receiving a clock signal, a first control input coupled to the first output of the comparator, a second control input coupled to the second output of the comparator, and an output coupled to the input of the oscillator.

11. A programmable analog array, comprising:

an array of cells, a plurality of cells in the array of cells including;

analog circuitry with variable connections and variable component values;

digital circuitry;

a memory unit for storing cell configuration data; and

switch circuitry, wherein the switch circuitry configures the analog circuitry and the digital circuitry in accordance with the cell configuration data;

interconnection circuitry coupled to the array of cells, wherein the interconnection circuitry enables an interconnection of a cell in the array of cells with at least one other cell in the array of cells;

a local feedback loop established between said analog circuitry and said digital circuitry within the array of cells; and

an accessing circuit coupled to the interconnection circuitry, wherein the accessing circuit selectively accesses said cell in the array of cells, transmits the cell configuration data to the cell to internally configure the cell as one of the plurality of circuit functions, and transmits interconnection data to the interconnection circuitry.

12. The programmable analog array of claim 11, wherein the local feedback loop is established between a first cell of the plurality of cells and a second cell of the plurality of cells, digital circuitry of the second cell converts an analog signal received from analog circuitry of the first cell to digital information for altering the variable connections and adjusting the variable component values of the analog circuitry of the first cell.

13. The programmable analog array of claim 11, wherein the accessing circuit includes a data storage element for storing the cell configuration data for said first cell of the array of cells and for storing the interconnection data.

14. A method for establishing a feedback loop, comprising the steps of:

forming an array of cells;

forming analog circuitry in first cells in the array of cells;

forming digital circuitry in second cells in the array of cells;

configuring the analog circuitry and the digital circuitry in a first selected cell and a second selected cell in the array of cells, respectively,

generating an analog signal in the analog circuitry in the first selected cell;

transmitting the analog signal directly to the digital circuitry in the second selected cell;

generating digital control information using the analog signal;

transmitting the digital control information directly to the analog circuitry in the first selected cell; and

altering variable connections and adjusting component values of the analog circuitry in the first selected cell in accordance with the digital control information.

15. The method for establishing a feedback loop as claimed in claim 14, further comprising the step of interconnecting the first selected cell to the second selected cell.

16. The method for establishing a feedback loop as claimed in claim 14, wherein the first selected cell is the same cell as the second selected cell.

17. The method for establishing a feedback loop as claimed in claim 14, wherein the step of configuring the analog circuitry and the digital circuitry includes the steps of:

storing cell configuration data in a memory unit; and

configuring the analog circuitry and the digital circuitry in accordance with the cell configuration data stored in the memory unit.

18. The method for establishing a feedback loop as claimed in claim 14, further comprising the steps of:

generating a second analog signal in the analog circuitry in the second selected cell; and

transmitting the second analog signal directly to the digital circuitry in the first selected cell.

19. The method for establishing a feedback loop as claimed in claim 14, wherein the step of configuring the analog circuitry and digital circuitry includes the steps of:

configuring an amplifier from the analog circuitry of the first selected cell, wherein the amplifier has an input for receiving an input signal;

configuring a peak detector from the analog circuitry of the second selected cell;

coupling an input of the peak detector to an output of the amplifier;

configuring a comparator from the analog circuitry of the first selected cell, wherein the comparator has a non-inverting input coupled for receiving a reference voltage;

coupling an inverting input of the comparator to an output of the peak detector;

configuring a counter from the digital circuitry of the first selected cell, wherein the counter has a clock input coupled for receiving a clock signal;

coupling a first control input of the counter to a first output of the comparator;

coupling a second control input of the counter to a second output of the comparator; and

coupling an output of the counter to a control input of the amplifier for adjusting a gain of the amplifier by reconfiguring the amplifier.

20. The method for establishing a feedback loop as claimed in claim 14, wherein the step of configuring the analog circuitry and the digital circuitry includes the steps of:

configuring an oscillator from the analog circuitry of the first selected cell;

configuring a first counter from the digital circuitry of the second selected cell, wherein the first counter has a control input coupled for receiving a first voltage;

coupling a clock input of the first counter to an output of the oscillator;

configuring a multiplexer from the digital circuitry of the second selected cell;

coupling an input of the multiplexer to an output of the first counter;

configuring a logic gate from the digital circuitry of the second selected cell, wherein the logic gate has a first input coupled for receiving an input signal;

coupling a second input of the logic gate to an output of the multiplexer;

configuring a filter from the analog circuitry of the second selected cell;

coupling an input of the filter to an output of the logic gate;

configuring a comparator from the analog circuitry of the first selected cell, wherein the comparator has an inverting input coupled for receiving a reference voltage;

coupling a non-inverting input of the comparator to an output of the filter;

configuring a second counter from the digital circuitry of the first selected cell, wherein the second counter has a clock input coupled for receiving a clock signal;

coupling a first control input of the second counter to a first output of the comparator;

coupling a second control input of the second counter to a second output of the comparator; and

coupling an output of the second counter to a control input of the oscillator for adjusting a frequency of the oscillator by reconfiguring the oscillator.