Method for entering state flow diagrams using schematic editor programs

• US 5,691,912 A
• Filed: 06/05/1995
• Issued: 11/25/1997
• Est. Priority Date: 07/30/1993
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Duncan, Robert G.
• Primary Examiner(s): Trans, Vincent N.
• Application Number:
  US08/465,635
• Time in Patent Office: 904 Days
• Field of Search: 364/488, 364/489, 364/490, 364/491
• US Class Current: 716/102
• CPC Class Codes: G06F 30/30 Circuit design

Abstract

A system and method for entering a circuit design into a computer using a schematic capture package. The schematic capture package is modified to include a library of state flow components represented by symbols which can be connected to produce a desired representation of the circuit design. The system allows a circuit design to be displayed on a video terminal using both state flow diagram and the schematic diagram symbols, with terminals of the state flow symbols connecting to terminals of the schematic symbols. The state flow diagram using state flow symbols is combined with a schematic diagram including schematic symbols to generate a netlist representing the combined circuit.

Claims

1. A computer readable medium storing an executable schematic capture program, the program having sequences of instructions which, when executed by a processor, cause the processor to perform the following steps:

forming a state flow diagram on a computer video terminal in response to a user selecting state flow components from a library and connecting the state flow components by flow bus segments, each state flow component in the library including a state flow symbol and an underlying circuit design, the library comprising at least one spawn state flow component connectable to at least two other state flow components, wherein states represented by each of the other state flow components are independent and simultaneously active; and

generating a netlist from netlists for underlying circuit designs of each of the state flow symbols and connections indicated by the flow bus segments.

2. The computer readable medium of claim 1, wherein the sequences of instructions further cause the processor to perform the step of forming a circuit diagram on the video terminal in response to the user selecting schematic components from a library and connecting the schematic components by signal lines, each schematic component including an underlying circuit design and a schematic symbol, and wherein the netlist is further generated from netlists for underlying circuit designs of each of the schematic symbols, the netlist including at least one connection between one of the state flow components and one of the schematic components.

3. The computer readable medium of claim 2, wherein the schematic components and state flow components are part of the same library.

4. An integrated circuit produced by:

forming on a computer video terminal a state flow diagram representative of a state machine in response to a user selecting state flow components from a library and connecting the state flow components by flow bus segments, each state flow component in the library including a state flow symbol and an underlying circuit design, the library comprising at least one spawn state flow component connectable to at least two other state flow components wherein states represented by each of the other state flow components are independent and simultaneously active;

generating a netlist incorporating underlying circuit designs of each of the state flow symbols as connected by the flow bus segments; and

configuring an integrated circuit device using the netlist so as to implement the state machine, whereby the state machine transitions through independent sequences of states simultaneously.

5. In a computer system having a memory device, a computer implemented process for generating a netlist for a circuit design for a state machine having multiple active states, the process comprising the steps of:

receiving and storing on the memory device a first portion of the circuit design comprising a plurality of state flow components connected by flow bus segments, each state flow component including a state flow symbol and an underlying circuit design, the plurality of state flow components comprising at least one spawn state flow component connectable to at least two other state flow components wherein states represented by each of the other state flow components are independent and simultaneously active; and

generating a netlist including netlists for underlying circuit designs of each of the state flow symbols as connected by the flow bus segments.

6. The process of claim 5, further comprising the step of receiving and storing on the memory device a second portion of the circuit design comprising a plurality of schematic components, each schematic component including an underlying circuit design and a schematic symbol, and wherein the netlist comprises netlists for underlying circuit designs of each of the schematic symbols, the netlist including at least one connection between one of the state flow components and one of the schematic components.