Method and system for performance monitoring of dispatch unit efficiency in a processing system

• US 5,691,920 A
• Filed: 10/02/1995
• Issued: 11/25/1997
• Est. Priority Date: 10/02/1995
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Levine, Frank Eliot, Welbon, Edward Hugh, Roth, Charles Philip
• Primary Examiner(s): Voeltz, Emanuel T.
• Assistant Examiner(s): ASSOUAD, PATRICK J
• Application Number:
  US08/538,070
• Time in Patent Office: 785 Days
• Field of Search: 364/551.01, 364/550, 395/180, 395/184.01, 371/22.5, 371/22.6, 371/28
• US Class Current: 702/186
• CPC Class Codes: G06F 11/3409 for performance assessment
• CPC Class Codes: G06F 11/3423 where the assessed time is active or idle time
• CPC Class Codes: G06F 11/3476 Data logging G06F11/14, G06F11/2205 take precedence
• CPC Class Codes: G06F 11/348 Circuit details, i.e. tracer hardware
• CPC Class Codes: G06F 2201/86 Event-based monitoring
• CPC Class Codes: G06F 2201/88 Monitoring involving counting
• CPC Class Codes: G06F 2201/885 Monitoring specific for caches

Abstract

A method and system for determining the efficiency of operation of a dispatch unit in a processing system, the processing system including at least one performance monitor counter (PMC) and at least one monitor mode control register (MMCR) to configure the operations of the at least one PMC, includes counting a number of instructions dispatched by the dispatch unit during a predetermined sampling period, counting a number of times a predetermined number of instructions are dispatched by the dispatch unit per cycle during the predetermined sampling period, and determining the efficiency of the dispatch unit according to the counted number of instructions and the counted number of times the predetermined number of instructions are dispatched by the dispatch unit.

Claims

1. A method for determining the efficiency of operation of a dispatch unit in a processing system, the processing system including special purpose registers, one or more of the special purpose registers designated as at least one performance monitor counter (PMC) and at least one monitor mode control register (MMCR) to configure the operations of the at least one PMC, the method comprising:

(a) counting a number of instructions dispatched by the dispatch unit during a predetermined sampling period;

(b) counting a number of times a predetermined number of instructions are dispatched by the dispatch unit per cycle during the predetermined sampling period; and

(c) determining the efficiency of the dispatch unit according to the counted number of instructions and the counted number of times the predetermined number of instructions are dispatched by the dispatch unit.

2. The method of claim 1 wherein the predetermined number of instructions is a maximum number of instructions that the processing system can dispatch per cycle.

3. The method of claim 1 wherein the predetermined number of instructions is less than a maximum number of instructions that the processing system can dispatch per cycle.

4. The method of claim 1 further comprising:

(d) altering at least one section of code to increase the efficiency of the dispatch unit according to the counted numbers.

5. The method of claim 1 further comprising:

(d) altering at least one hardware module to appropriately size the dispatch unit according to the counted numbers.

6. A system for determining the efficiency of operation of a dispatch unit in a processing system, the processing system including special purpose registers, one or more of the special purpose registers designated as at least one performance monitor counter (PMC) and at least one monitor mode control register (MMCR) to configure the operations of the at least one PMC, the system comprising a circuit for counting a number of instructions dispatched by the dispatch unit during a predetermined sampling period;

for counting a number of times a predetermined number of instructions are dispatched by the dispatch unit per cycle during the predetermined sampling period; and

for determining the efficiency of the dispatch unit according to the counted number of instructions and the counted number of times the predetermined number of instructions are dispatched by the dispatch unit.

7. The system of claim 6 wherein the predetermined number of instructions is a maximum number of instructions that the processing system can dispatch per cycle.

8. The system of claim 6 wherein the predetermined number of instructions is less than a maximum number of instructions that the SP system can dispatch per cycle.

9. The system of claim 6 in which the circuit further provides for altering at least one section of code to increase the efficiency of the dispatch unit according to the counted numbers.

10. The system of claim 6 in which the circuit further provides for altering at least one hardware module to appropriately size the dispatch unit according to the counted numbers.

11. A computer readable medium containing program instructions for determining the efficiency of operation of a dispatch unit in a processing system, the processing system including special purpose registers, one or more of the special purpose registers designated as at least one performance monitor counter (PMC) and at least one monitor mode control register (MMCR) to configure the operations of the at least one PMC, the instructions comprising:

(a) counting a number of instructions dispatched by the dispatch unit during a predetermined sampling period;

(b) counting a number of times a predetermined number of instructions are dispatched by the dispatch unit per cycle during the predetermined sampling period; and

(c) determining the efficiency of the dispatch unit according to the counted number of instructions and the counted number of times the predetermined number of instructions are dispatched by the dispatch unit.