Structure of split gate transistor for use in a non-volatile semiconductor memory and method of manufacturing such a split gate transistor

• US 5,691,937 A
• Filed: 08/21/1996
• Issued: 11/25/1997
• Est. Priority Date: 08/25/1995
• Status: Expired due to Fees

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Ohta, Noriyuki
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): MAI, SON LUU
• Application Number:
  US08/701,013
• Time in Patent Office: 461 Days
• Field of Search: 365/185.01, 365/185.1, 257/315, 257/316, 257/318, 257/319
• US Class Current: 365/185.01
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A non-volatile semiconductor memory is composed of split gate type memory cell transistors, each of which comprises a source region and a drain region formed at a principal surface of a semiconductor substrate, separately from each other to form a channel region between the source region and the drain region. This channel region is divided into a first channel region adjacent to the drain region and a second channel region adjacent to the source region. A first gate insulator film is formed on a surface of the first channel region, and a control gate electrode is formed on the first gate insulator film. An insulator layer is formed on the source region and the drain region, and a second gate insulator film is formed on an upper surface and a pair of opposite side surfaces of the control gate electrode and on a surface of the second channel region. A floating gate electrode is formed on the second gate insulator film to have opposite ends terminating on the insulator layer formed on the source region and the insulator layer formed on the drain region, respectively.

Claims

1. A non-volatile semiconductor memory composed of split gate type memory cell transistors each having a floating gate electrode and a control gate electrode, wherein each of the memory cell transistors comprises:

first and second source/drain regions formed at a principal surface of a semiconductor substrate, separately from each other, to form a channel region between said first and second source/drain regions, said channel region being divided into a first channel region adjacent to said first source/drain region and a second channel region adjacent to said second source/drain region;

a first gate insulator film formed on a surface of said first channel region;

a first gate electrode formed on said first gate insulator film and having a pair of opposite side surfaces, a first side surface of said pair of opposite side surfaces being adjacent said first source/drain region and a second side surface of said pair of opposite side surfaces being adjacent said second channel region;

an insulator layer formed on a surface of each of said first and second source/drain regions;

a second gate insulator film formed on an upper surface and said first and second side surfaces of said first gate electrode and on a surface of said second channel region; and

a second gate electrode formed on said second gate insulator film and having opposite ends terminating on said insulator layer formed on said surface of said first source/drain region and said insulator layer formed on said surface of said second source/drain region, respectively,

wherein one of said first and second gate electrodes constitutes the floating gate electrode, and the other of said first and second gate electrodes constitutes the control gate electrode.

2. The non-volatile semiconductor memory claimed in claim 1 wherein said insulator layer partially covers said first side surface of said first gate electrode, and said second gate insulator film covers a remaining portion of said first side surface of said first gate electrode and completely covers said second side surface of said first gate electrode opposite to said first side surface.

3. The non-volatile semiconductor memory claimed in claim 2 further including an interlayer insulator film formed to cover said second gate electrode and said insulator layer, and a digit line conductor formed on said interlayer insulator film and connected to said first source/drain region through a contact hole formed through said interlayer insulator to reach said first source/drain region.

4. A non-volatile semiconductor memory composed of split gate type memory cell transistors each having a floating gate electrode and a control gate electrode, wherein each of the memory cell transistors comprises:

first and second source/drain regions formed at a principal surface of a semiconductor substrate, separately from each other, to form a channel region between said first and second source/drain regions, said channel region being divided into a first channel region adjacent to said first source/drain region and a second channel region adjacent to said second source/drain region;

a first gate insulator film formed on a surface of said first channel region;

a first gate electrode formed on said first gate insulator film and having a pair of opposite side surfaces, a first side surface of said pair of opposite side surfaces being adjacent said second channel region and a second side surface of said pair of opposite side surfaces being adjacent said first source/drain region;

a second gate insulator film formed on said first gate electrode;

an insulator layer formed on a surface of each of said first and second source/drain regions;

a third gate insulator film formed to cover at least a surface of said second channel region and said first side surface; and

a second gate electrode formed on said second and third gate insulator films and having opposite ends terminating on said insulator layer formed on said surface of said first source/drain region and said insulator layer formed on said surface of said second source/drain region, respectively;

wherein one of said first and second gate electrodes constitutes the floating gate electrode, and the other of said first and second gate electrodes constitutes the control gate electrode.

5. The non-volatile semiconductor memory as claimed in claim 4, wherein said insulator layer formed on said surface of said first source/drain region completely covers said second side surface of said first gate electrode, and said third gate insulator film extends upward from said first side surface of said first gate electrode.

6. The non-volatile semiconductor memory claimed in claim 5 further including an interlayer insulator film formed to cover said second gate electrode and said insulator layer.

7. A method for manufacturing a non-volatile semiconductor memory composed of split gate type memory cell transistors each having a floating gate electrode and a control gate electrode, the method comprising the steps of:

(a) forming a first gate electrode on a first gate insulator film formed on a principal surface of a semiconductor substrate;

(b) forming first and second source/drain regions at said principal surface of said semiconductor substrate at opposite sides of said first gate electrode, in a self-alignment with said first gate electrode, so that a channel region is formed at said principal surface of said semiconductor substrate under said first gate electrode;

(c) forming an insulator layer to cover a surface of said first and second source/drain regions;

(d) removing an excess portion of said first gate electrode adjacent to said first source/drain region in a channel length direction, the remaining portion of said first gate electrode having a pair of opposite side surfaces, a first side surface of said pair of opposite side surfaces being adjacent said second source/drain region and a second side surface of said pair of opposite side surfaces being opposite said first side surface;

(e) forming a second gate insulator film on an upper surface and said first and second side surfaces of the remaining portion of said first gate electrode and on said principal surface of said semiconductor substrate from which said excess portion of said first gate electrode has been removed; and

(f) forming a second gate electrode to cover said second gate insulator film and to have opposite ends terminating on said insulator layer formed on said surface of said first source/drain region and said insulator layer formed on said surface of said second source/drain region, respectively,

wherein one of said first and second gate electrodes constitutes the floating gate electrode, and the other of said first and second gate electrodes constitutes the control gate electrode.

8. The method claimed in claim 7 wherein, in said step (c), said insulator layer is formed to partially cover said first side surface of said first gate electrode but said upper surface of said first gate electrode is put in an exposed condition, and

wherein, in said step (e), said second gate insulator film is formed to cover a remaining portion of said first side surface of said first gate electrode and to completely cover said second side surface of said first gate electrode.

9. The method claimed in claim 8 further including the steps of:

(g) forming an interlayer insulator film to cover said second gate electrode and said insulator layer; and

(h) forming a digit line conductor on said interlayer insulator film to be connected to said first source/drain region through a contact hole, which is formed through said interlayer insulator to reach said first source/drain region.

10. A method for manufacturing a non-volatile semiconductor memory composed of split gate type memory cell transistors each having a floating gate electrode and a control gate electrode, the method comprising the steps of:

(a) forming on a principal surface of a semiconductor substrate a stacked layer structure composed of a first gate insulator film, a first gate electrode, a second gate insulator film and a first portion of a second gate electrode portion, stacked in the named order;

(b) forming first and second source/drain regions at opposite sides of stacked layer structure, in a self-alignment with said stacked layer structure, so that a channel region is formed under said stacked layer structure;

(c) forming an insulator layer to cover a surface of said first and second source/drain regions;

(d) removing an excess portion of said stacked layer structure adjacent to said first source/drain region in a channel length direction;

(e) forming a third gate insulator film on at least a side surface of a remaining portion of said stacked layer structure and said principal surface of said semiconductor substrate from which said excess portion of said stacked layer structure has been removed;

(f) forming a second portion of said second gate electrode on said third gate insulator formed on said principal surface of said semiconductor substrate;

(g) forming a third portion of said second gate electrode to cover said second portion of said second gate electrode and said first portion of said second gate electrode of said remaining portion of said stacked layer structure and to have opposite ends respectively terminating on said insulator layer formed on said surface of said first source/drain region and said insulator layer formed on said surface of said second source/drain region,

wherein one of said first and second gate electrodes constitutes the floating gate electrode, and the other of said first and second gate electrodes constitutes the control gate electrode.

11. The method claimed in claim 10 wherein, in said step (c), said insulator layer is formed to partially cover a first side surface of said stacked layer structure but an upper surface of said stacked layer structure is put in an exposed condition;

and

wherein, in said step (e), said third gate insulator film is formed to cover an upper surface of the remaining stacked layer structure, a remaining portion of said first side surface of said stacked layer structure and a whole of a second side surface of said stacked layer structure opposite to said first side surface, and said principal surface of said semiconductor substrate from which said excess portion of said first gate electrode has been removed, and then, said third gate insulator film formed to cover said upper surface of the remaining stacked layer structure is selectively removed so that a surface of said first portion of said second gate electrode in the remaining portion of said stacked layer structure is exposed.

12. The method claimed in claim 11 further including the step of:

(h) forming an interlayer insulator film to cover said second gate electrode and said insulator layer.