Configurable digital signal interface using field programmable gate array to reformat data

• US 5,692,159 A
• Filed: 05/19/1995
• Issued: 11/25/1997
• Est. Priority Date: 05/19/1995
• Status: Expired due to Term

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Digital Equipment Corporation (HP Inc.)
• Inventors: Shand, Mark A.
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): Fiul, Dan
• Application Number:
  US08/444,453
• Time in Patent Office: 921 Days
• Field of Search: 395/200.2, 395/500, 395/386, 395/898, 395/886, 395/200.18, 395/200.01, 375/377, 341/107, 326/38, 340/576, 342/70
• US Class Current: 703/27
• CPC Class Codes: G06F 5/00 Methods or arrangements for data conversion without changing the order or content of the data handled

Abstract

A field programmable gate array is configured to interface a source of externally produced input digital signals to a host computer system. The input signals having a first data type are reformatted to output digital signals having a second data type compatible with the computer system. The computer system can be used for storing and processing the output digital signals. The interface includes a first set of registers connected to the external source. The first set of registers store first portions of the input digital signals. A first buffer connected to the first set of registers store a combination of the first portions of the input digital signals, the combination of the first portions of the input digital signals stored in the first buffer formatted according to the second data type. The interface also includes a direct memory access controller to transport the combinations of the first portions of the input digital signals as output digital signals to the memory of the computer system.

Claims

1. An apparatus for reformatting input signals to be compatible with a computer system, comprising:

a first set of combinations registers to store first portions of the input signals, each of the input signals having a first data type compatible with a source external to the computer system, being formed of a first portion combined with a second portion, and having a length different than a length of a second data type compatible with the computer system;

a first buffer to store a first combination of the first portions stored in the first set of registers, the first combination having the second data type; and

a controller to control transport of the first combination as output signals from the first buffer to a memory of the computer system.

2. The apparatus of claim 1 further comprising:

a second set of registers to store the second portions of the input signals;

a second buffer to store a second combination of the second portions stored in the second set of registers, the second combination having the second data type;

wherein the controller is configured to control transport of the second combination as the output signals from the second buffer to the memory of the computer system.

3. The apparatus of claim 2 further comprising:

a first control command block to indicate a length, a status, and a destination address of the first combination.

4. The apparatus of claim 3 further comprising:

a second control command block to indicate a length, a status, and a destination address of the second combination.

5. The apparatus of claim 4 including means for filling the second buffer with the second combination while transporting the first combination from the first buffer.

6. The apparatus of claim 2 wherein the first data type has a length of ten bits, and the second data type has a length of eight.

7. The apparatus of claim 2 wherein the input signals are received while the output signals are transported.

8. The apparatus of claim 7 wherein the source is a CCD camera producing ten bit pixels as input signals, and the second data type formats signals as eight bit bytes.

9. An apparatus for reformatting input signals having an input data type compatible with a source of the input signals to be compatible with a computer system external to the source, comprising:

a first transport channel configured to transport first portions of the input signals, the first portions having a first output data type compatible with the computer system;

a second transport channel configured to transport second portions of the input signals, the second portions having a second output data type compatible with the computer system;

wherein, each of the input signals is formed of a first signal portion combined with a second signal portion, and has a length different than a length of a signal compatible with the computer system.

10. The apparatus of claim 9 wherein:

the first transport channel includes a first set of registers and a first buffer configured to store the first portions of the input signals, and

the second transport channel includes a second set of registers and a second buffer configured to store the second portions of the input signals, and

further comprising a controller to control transport of the first portions from the first buffer to a memory of the computer system and transport of the second portions from the second buffer to the memory of the computer system.

11. The apparatus of claim 10 wherein the input data type is expressed in ten bits, the first output data type is expressed in eight bits, and the second output data type is expressed in two bits.

12. The apparatus of claim 10 wherein the input data type is expressed in twelve bits, the first output data type is expressed in eight bits, and the second output data type is expressed in four bits.

13. A method for reformatting signals to be compatible with a computer system, comprising the steps of:

receiving input signals having an input data type compatible with a source of the input signals, the source of the input signals external to the computer system,

transporting first portions of the input signals along a first transport channel, the first portions having a first output data type compatible with the computer system,

transporting second portions of the input signals along a second transport channel, the second portions of the input signals having a second output data type compatible with the computer system;

wherein, each of the input signals is formed of a first signal portion combined with a second signal portion, and has a length different than a length of a signal compatible with the computer system.

14. An interface for reformatting input signals, each input signal having a first bit length, to be compatible with a computer system formatted to process words of a second bit length which is different than the first bit length, comprising:

a set of registers, each register in said set being configured to store a respective one of the input signals such that a total bit length of stored input signals in the set of registers equals the second bit length;

a first buffer configured to receive first stored input signals having the second bit length in parallel from the set of registers and to store the received first stored input signals;

a second buffer configured to receive second stored input signals having the second bit length in parallel from the set of registers and to store the received second stored input signals; and

a controller configured to control the receipt of the first stored input signals by the first buffer and the second stored input signals by the second buffer, and to control transport of the received first stored input signals as output from the first buffer and the received second stored input signals as output from the second buffer to a memory of the computer system such that the transport of the received first stored input signals as output from the first buffer occurs simultaneous with receipt of the second stored input signals as input to the second buffer from the set of registers and the received first and the received second stored input signals are transported from the first and the second buffers as reformatted signals compatible with the computer system.

15. An interface according to claim 14, wherein the input signals are serial input signals and the second bit length is in a power of two increment of the first bit length.

16. An interface according to claim 14, further comprising:

a null generator for generating null input signals, each null input signal having a third bit length;

wherein each said register is configured to store the respective one of the input signals in combination with a respective one of the null input signals such that the total bit length of stored input signals in the set of registers equals the second bit length.

17. An interface for reformatting input signals, each input signal having a first bit length, to be compatible with a computer system formatted to process words of a second bit length which is different than the first bit length, comprising:

a first set of registers, each register within said first set being configured to store a first portion of a respective one of the input signals such that a total bit length of stored first portions in the first set of registers equals the second bit length;

a second set of registers, each register within said second set being configured to store a second portion of a respective one of the input signals, such that a total bit length of stored second portions in the second set of registers equals the second bit length;

a first buffer configured to receive the stored first portions in parallel from the first set of registers and to store the received first portions;

a second buffer configured to receive the stored second portions in parallel from the second set of registers and to store the received second portions; and

a controller configured to control transport of the first portions as output from the first buffer to a memory of the computer system and transport of the second portions as output from the second buffer to the memory of the computer system , the transported first and second portions being reformatted signals compatible with the computer system.

18. An interface according to claim 17, wherein the input signals are serial input signals and the second bit length is in a power of two increment of the first bit length.

19. An interface according to claim 17, wherein each first portion has a third bit length and each second portion has a fourth bit length and only the first, the third and the fourth bit lengths are expressible as a power of two number.

20. An interface according to claim 17, wherein the first set of registers includes a first number of registers and the second set of registers includes a second number of registers different than the first number of registers.

21. A field programmable gate array for reformatting input signals, each input signal having a first bit length, to be compatible with a computer system formatted to process words of a second bit length which is different than the first bit length, comprising:

a set of registers, each register being selectively configurable to store (i), in a first programmed configuration, a respective one of the input signals such that a total bit length of stored input signals in the set of registers equals the second bit length and (ii) in a second programmed configuration, only a portion of a respective one of the input signals such that a total bit length of stored portions in the set of registers equals the second bit length, and thereby reformat the input signals to be compatible with the computer system;

a first buffer configurable to (i), in the first programmed configuration, receive first stored input signals having the second bit length in parallel from the set of registers and to store the first stored input signals and (ii), in the second programmed configuration, to receive the stored first portions in parallel from the set of registers and to store the received first portions;

a second buffer configurable (i), in the first programmed configuration, to receive second stored input signals having the second bit length in parallel from the set of registers and to store the second stored input signals and (ii), in the second programmed configuration, to receive second portions of the input signals from a second set of registers and to store the received second portions; and

a controller configurable to control (i), in the a first programmed configuration, transport of the first stored input signals as output from the first buffer to a memory of the computer system and to control simultaneous receipt of the second stored input signals as input to the second buffer from the set of registers and (ii), in the second programmed configuration, transport of the first portions as output from the first buffer to the memory of the computer system and transport of the second portions as output from the second buffer to the memory of the computer system.