Personal digital assistant module having a host interconnect bus without an interrupt line and which handles interrupts as addresses associated with specific interrupts in memory
First Claim
1. A digital assistant module comprising:
- an internal bus having address lines, data lines, and control signal lines, but no interrupt control lines;
a bus controller adapted to provide bus cycles, including address cycles;
a CPU connected to the bus;
a memory connected to the bus;
a video display coupled to the bus;
input apparatus coupled to the bus; and
an interrupt controller connected to the bus;
wherein interrupts are mapped in high memory as unused addresses, and the interrupt controller is adapted to compare addresses during address cycles with the memory-mapped interrupts, and to interrupt the CPU in those instances wherein an address on the address bus matches an address reserved as an interrupt.
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Abstract
A personal digital assistant module with a local CPU, memory, and I/O interface has a host interface comprising a bus connected to the local CPU and a connector at a surface of the personal digital assistant for interfacing to a bus connector of a host general-purpose computer, providing direct bus communication between the personal digital assistant and the host general-purpose computer. In an embodiment, the personal digital assistant also stores a security code. The personal digital assistant according to the invention forms a host/satellite combination with a host computer having a docking bay, wherein upon docking a docking protocol controls access by the host to memory of the personal digital assistant based on one or more passwords provided by a user to the host. In another embodiment the personal digital assistant also has an expansion port connected to the local CPU, and expansion peripheral devices may be connected and operated through the expansion port.
58 Citations
12 Claims
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1. A digital assistant module comprising:
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an internal bus having address lines, data lines, and control signal lines, but no interrupt control lines; a bus controller adapted to provide bus cycles, including address cycles; a CPU connected to the bus; a memory connected to the bus; a video display coupled to the bus; input apparatus coupled to the bus; and an interrupt controller connected to the bus; wherein interrupts are mapped in high memory as unused addresses, and the interrupt controller is adapted to compare addresses during address cycles with the memory-mapped interrupts, and to interrupt the CPU in those instances wherein an address on the address bus matches an address reserved as an interrupt. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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Specification