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Personal digital assistant module having a host interconnect bus without an interrupt line and which handles interrupts as addresses associated with specific interrupts in memory

  • US 5,692,199 A
  • Filed: 03/11/1997
  • Issued: 11/25/1997
  • Est. Priority Date: 10/28/1993
  • Status: Expired due to Fees
First Claim
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1. A digital assistant module comprising:

  • an internal bus having address lines, data lines, and control signal lines, but no interrupt control lines;

    a bus controller adapted to provide bus cycles, including address cycles;

    a CPU connected to the bus;

    a memory connected to the bus;

    a video display coupled to the bus;

    input apparatus coupled to the bus; and

    an interrupt controller connected to the bus;

    wherein interrupts are mapped in high memory as unused addresses, and the interrupt controller is adapted to compare addresses during address cycles with the memory-mapped interrupts, and to interrupt the CPU in those instances wherein an address on the address bus matches an address reserved as an interrupt.

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