Etch stop for copper damascene process

• US 5,693,563 A
• Filed: 07/15/1996
• Issued: 12/02/1997
• Est. Priority Date: 07/15/1996
• Status: Expired due to Fees

• Current Assignee: Chartered Semiconductor Manufacturing Incorporated (Mamoura Diversified Global Holding PJSC)
• Original Assignee: Chartered Semiconductor Manufacturing Incorporated (Mamoura Diversified Global Holding PJSC)
• Inventors: Teong, Su-Ping
• Primary Examiner(s): Niebling, John
• Assistant Examiner(s): Mee, Brendan
• Application Number:
  US08/679,973
• Time in Patent Office: 505 Days
• Field of Search: 437/190, 437/195, 437/198, 257/758
• US Class Current: 438/627
• CPC Class Codes: G11B 17/02 Details
• CPC Class Codes: G11B 23/0021 discs
• CPC Class Codes: H01L 21/76808 involving intermediate temporary filling with material
• CPC Class Codes: H01L 2221/1031 Dual damascene by forming vias in the via-level dielectric prior to deposition of the trench-level dielectric
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

The invention describes the application of copper damascene connectors to a double level metal process. A dual damascene copper connector whose upper surface is coplanar with the upper surface of the insulating layer in which it is embedded is described. Out-diffusion of copper from the connector is prevented by at least two barrier layers. One or two barrier layers are located at the interface between the connector and the insulating layer while another barrier layer comprises conductive material and covers the upper surface of the connector. When a second damascene connector is formed above the first connector the conductive barrier layer facilitates good contact between the two connectors. It also acts as an etch stop layer during the formation of the second connector. A process for manufacturing this structure is also described. It involves over-filling a trench in the surface of the insulator with copper and then removing the excess by chem.-mech. polishing.

Claims

1. A method for manufacturing a double layered copper connector comprising:

(a) providing a partially completed integrated circuit;

(b) depositing a first insulating layer, having an upper surface, on said integrated circuit;

(c) patterning and then etching said first insulating layer to form a cavity extending down to the level of said integrated circuit;

(d) depositing a first barrier layer on the walls of said cavity and on the upper surface said first insulating layer;

(e) patterning and etching said first barrier layer so that it extends for some distance, on the upper surface of said first insulating layer, on all sides of the cavity;

(f) depositing a second insulating layer, having upper and lower surfaces, on the upper surface of said first insulating layer;

(g) patterning and then etching said second insulating layer to form a trench therein, said trench being narrower than said extension of the first barrier layer, wider than said cavity, and symmetrically disposed over said cavity;

(h) depositing a second barrier layer on the walls of both the trench and the cavity and on the upper surface of said second insulating layer;

(i) depositing a copper layer to more than fill said cavity and said trench;

(j) removing said copper layer and said second barrier layer to the level of the upper surface of said second insulating layer, thereby forming a first dual damscene copper connector having an upper surface;

(k) depositing an etch stop barrier layer on the upper surface of the second insulating layer and on the upper surface of said damascene connector;

(l) patterning and etching said etch stop barrier layer so that it slightly overlaps said upper surface of said damascene connector; and

(m) forming a second dual damascene connector, disposed directly above the first dual damascene connector, in the manner recited in steps (b) through (j) above.

2. The method of claim 1 wherein the method for removing said copper layer comprises chemical-mechanical polishing.

3. The method of claim 1 wherein the method for depositing said copper layer comprises vacuum evaporation or chemical vapor deposition.

4. The method of claim 1 wherein said first barrier layer is deposited to a thickness between about 500 and 2,000 Angstroms.

5. The method of claim 1 wherein said second barrier layer is deposited to a thickness between about 500 and 2,000 Angstroms.

6. The method of claim 1 wherein said etch stop barrier layer is deposited to a thickness between about 500 and 1,500 Angstroms.

7. The method of claim 1 wherein the distance that the first barrier layer extends on the upper surface of the first insulating layer is between about 0.1 and 0.5 microns.