Process for the laminar joining of silicon semiconductor slices

• US 5,693,574 A
• Filed: 02/04/1994
• Issued: 12/02/1997
• Est. Priority Date: 02/22/1991
• Status: Expired due to Term

• Current Assignee: Deutsche Aerospace AG (Mercedes-Benz Group AG)
• Original Assignee: Deutsche Aerospace AG (Mercedes-Benz Group AG)
• Inventors: Panitsch, Klaus, Schuster, Gunther
• Primary Examiner(s): TRINH, MICHAEL MANH
• Application Number:
  US08/192,329
• Time in Patent Office: 1,397 Days
• Field of Search: 437/225, 437/226, 437/233, 437/235, 437/974, 437/927, 148/DIG. 12, 148/DIG. 58, 148/DIG. 59
• US Class Current: 438/406
• CPC Class Codes: H01L 2224/29117 the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
• CPC Class Codes: H01L 2224/29124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/83805 involving forming a eutectic alloy at the bonding interface
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01032 Germanium [Ge]
• CPC Class Codes: Y10S 148/012 Bonding, e.g. electrostatic for strain gauges
• CPC Class Codes: Y10S 148/058 Ge germanium

Abstract

A process for the laminar joining of two or more silicon semiconductor slices (wafers) under the effect of pressure and heat, in which a thin layer of a semiconductor-compatible material is applied to at least one of the surfaces to be joined.

Claims

1. Process for laminar joining of at least two silicon semiconductor slices, each having a front side and a back side, under the effect of heat, with microelectronic components being integrated in a recess in the front side of one of said silicon semiconductor slices, said process comprising the steps of:

applying a first layer of aluminum to a front side of each of said silicon semiconductor slices;

applying a second layer of germanium on top of said first layer of each of said silicon semiconductor slices, said first and second layers having an overall thickness of less than 10 μ

m;

stacking said silicon semiconductor slices on top of one another with the front sides thereof facing one another;

causing said first and second layers to combine to form a eutectic alloy joining layer between said silicon semiconductor slices, by simultaneously applying heat and pressure to said silicon semiconductor slices.

2. Process according to claim 1, wherein the thickness of the first and second layers are less than 5μ

.

3. Process according to claim 1 further comprising the step of applying an intermediate layer between said first layer and said front side of at least one of said silicon semiconductor slices, said intermediate layer comprising a material selected from the group consisting of a dielectric insulator material and a metallic material.

4. Process according to claim 1, wherein said first and second applying steps are performed by a physical or chemical precipitation process, in the presence of a vacuum.

5. A process for laminar joining of at least two silicon slices, at least one of which has microelectronic components arranged in a recess therein and each of which has a first layer comprising aluminum on a surface thereof and a second layer comprising germanium on top of said first layer, said process comprising the steps of:

placing said silicon slices in contact with one another, with said first and second layers and disposed therebetween;

applying a contact pressure to said silicon slices; and

heating said silicon slices and layers while applying said contact pressure.