Combined trench and field isolation structure for semiconductor devices

• US 5,693,971 A
• Filed: 07/14/1994
• Issued: 12/02/1997
• Est. Priority Date: 07/14/1994
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Gonzalez, Fernando
• Primary Examiner(s): Saadat, Mahshid D.
• Assistant Examiner(s): Wallace, Valencia Martin
• Application Number:
  US08/276,511
• Time in Patent Office: 1,237 Days
• Field of Search: 257/68, 257/71, 257/296, 257/301, 257/304, 257/314, 257/315, 257/320, 257/305, 437/52
• US Class Current: 257/314
• CPC Class Codes: H01L 21/763 Polycrystalline semiconductor regions H01L21/76264 takes precedence
• CPC Class Codes: H01L 21/765 by field effect H01L21/76264 takes precedence
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor
• CPC Class Codes: H10B 12/31 having a storage electrode stacked over the transistor

Abstract

An isolation structure providing electrical isolation in two dimensions between memory cells in semiconductor memory devices. The isolation structure comprises a trench formed in a substrate of a semiconductor memory device such as a Dynamic Random Access Memory (DRAM). The trench is lined with an insulating material and filled with polysilicon to form a floating gate. An electrical charge is then injected into the polysilicon floating gate. The isolation structure is located between memory cells in an array to provide isolation between cells in sub-micron spacing by combining the characteristics of trench and field isolation. The electrical charge is injected into the polysilicon floating gate by applying a charging voltage to the wordlines of the memory cell array. The charging voltage is applied periodically as necessary to maintain effective isolation. Two dimensional isolation is achieved by extending the trench to surround each pair of memory cells sharing a common bitline contact.

Claims

1. An isolation structure for semiconductor devices, which comprises a trench in a substrate, a body of electrically charged polysilicon in the trench, and insulating material completely surrounding the body of polysilicon.

2. An isolation structure for semiconductor devices, which comprises:

a. a substrate;

b. a trench in the substrate;

c. first insulating material lining the trench;

d. a body of polysilicon filling the lined trench;

e. second insulating material overlaying the floating gate so that the body of polysilicon is completely surrounded by the first and second insulating materials, the body of polysilicon therein defining a floating gate;

f. a layer of polysilicon overlaying at least a portion of the second insulating material above the floating gate; and

g. a charging means comprising;

1) a sensing circuit for sensing the charge on the floating gate;

2) a booting circuit for applying a charging voltage to the layer of polysilicon; and

3) a switching circuit for connecting the layer of polysilicon to the booting circuit when the charge on the floating gate is equal to or less than a predetermined level.

3. An isolation structure according to claim 2, wherein the charging means further comprises Fowler-Nordheim currents.

4. An isolation structure according to claim 2, wherein the first insulating material has a thickness of 80-200 angstroms and the second insulating material has a thickness of 200-500 angstroms.

5. An isolation structure according to claim 2, wherein the charging voltage is 9-13 volts.

6. An isolation structure according to claim 2, wherein the layer of polysilicon is a wordline in a memory cell array having a plurality of wordlines and a plurality of bitlines arranged generally perpendicular to one another over the substrate and the switching circuit connects the wordlines to the booting circuit when the charge on the floating gate is equal to or less than the predetermined level and connects the wordlines to an operating circuit when the charge on the floating gate is greater than the predetermined level.

7. A semiconductor device, which comprises a substrate having element forming regions on which semiconductor elements are formed and an isolation structure surrounding each element forming region to provide a plurality of element forming regions electrically isolated from each other, the isolation structure comprising a trench in the substrate, a body of electrically charged polysilicon in the trench, and insulating material completely surrounding the body of polysilicon.

8. A semiconductor device, which comprises:

a. a substrate;

b. a plurality of wordlines arranged parallel to each other and extending in a row direction above the substrate;

c. a plurality of bitlines arranged parallel to each other and extending in a column direction generally perpendicular to and above the wordlines;

d. an isolation structure comprising a trench in the substrate, a body of electrically charged polysilicon in the trench, and insulating material completely surrounding the body of polysilicon, the polysilicon therein defining a floating gate; and

e. the trench being located beneath and between multiple wordlines in the column direction.

9. A semiconductor device according to claim 8, further comprising:

a) an array of memory cells wherein each memory cell includes one transistor and one capacitor;

b) each transistor having a gate electrode on a gate insulator, the gate electrode comprising a portion of a first wordline located between the isolation structure and a bitline contact, and source and drain regions formed in the surface of the substrate at both sides of the gate electrode, one of the source and drain regions being connected to the bitline contact and the other of the source and drain regions adjoining the isolation structure;

c) each capacitor having a bottom electrode connected to the source and drain region adjoining the isolation structure and overlaying a second wordline located above one side of the isolation structure and overlaying the gate electrode, an insulating layer interposed between the bottom electrode and the second wordline, an insulating layer interposed between the bottom electrode and the gate electrode, a top electrode above the bottom electrode, and a cell dielectric layer interposed between the top and bottom electrodes; and

d) wherein the isolation structure, which is located beneath and between the second wordlines in adjacent memory cells, provides electrical isolation between the adjacent memory cells.

10. A semiconductor device according to claim 9, wherein the isolation structure surrounds first and second memory cells having a shared bitline contact therebetween.

11. An isolation structure according to claim 9, further comprising a charging means for injecting an electrical charge into the floating gate.

12. An isolation structure according to claim 11, wherein the charging means comprises:

a) a sensing circuit connected to the source and drain region adjoining the isolation structure to detect current passing through the transistor when a threshold voltage is applied to the gate electrode;

b) a booting circuit for applying a charging voltage to the floating gate; and

c) a switching circuit connected to the sensing circuit and the booting circuit for connecting the floating gate to the booting circuit as long as current passes through the transistor when the threshold voltage is applied to the gate electrode.