Multiprobing semiconductor test method for testing a plurality of chips simultaneously

• US 5,694,050 A
• Filed: 03/08/1996
• Issued: 12/02/1997
• Est. Priority Date: 11/30/1992
• Status: Expired due to Fees

• Current Assignee: Tokyo Seimitsu Company Limited
• Original Assignee: Tokyo Seimitsu Company Limited
• Inventors: Noguchi, Etsuo
• Primary Examiner(s): Nguyen, Vinh P.
• Application Number:
  US08/612,760
• Time in Patent Office: 634 Days
• Field of Search: 324/754, 324/72.5, 324/73.1, 324/158.1, 324/765, 324/760, 437/8, 257/40, 257/48
• US Class Current: 324/754.07
• CPC Class Codes: G01R 1/06705 Apparatus for holding or moving single probes for moving multiple probe heads or ICs under test G01R31/2886

Abstract

The purpose of the test method is to improve test efficiency in a semiconductor test method utilizing multiprobing. The semiconductor test method involves placing probes into contact with the electrode pads of semiconductor chips on a semiconductor wafer with a test head providing and receiving test signals through the probes thereby checking the electrical properties of the semiconductor chips sequentially. According to the test method, in order to test a plurality of adjacent semiconductor chips simultaneously, as many probes are provided as the number of semiconductor chips to be tested simultaneously, the test head is capable of providing and receiving test signals for the plurality of semiconductor chips simultaneously, and the number of semiconductor chips that are tested simultaneously is determined without being limited to a power of 2.

Claims

1. In semiconductor test equipment, in which probes are placed into contact with the electrode pads of semiconductor chips on a semiconductor wafer and a test head provides and receives test signals through said probes thereby checking the electrical properties of said semiconductor chips sequentially, a multiprobing semiconductor test method comprising the steps of:

to test a plurality of adjacent semiconductor chips simultaneously, providing as many probes as the number of semiconductor chips to be tested simultaneously;

providing said test head which is capable of providing and receiving test signals for said plurality of semiconductor chips simultaneously; and

dividing each column of chips into groups, said column extending along the direction that said semiconductor chips to be tested simultaneously are arranged, each group being for simultaneous testing, when the number of groups in adjacent columns is different, displacing a center position of one of the groups in the adjacent column from a corresponding center position of a group in the other adjacent column such that the groups are not arranged in a straight line in a row direction with a group in an adjacent column, and when the number of groups in adjacent columns is the same, the center position of groups in adjacent columns are arranged adjacently such that the groups are arranged in a straight line in a row direction with a group in an adjacent column.

2. Multiprobing semiconductor test method according to claim 1, wherein said step of dividing each said column of chips into groups each for simultaneous testing, further comprising the step of determining a difference in the number of semiconductor chips between the groups at both ends of said column to be not greater than 1.

3. A multiprobing semiconductor test method for semiconductor test equipment, said semiconductor test equipment having probes and a test head, said probes being placed into contact with electrode pads of semiconductor chips on a semiconductor wafer, said test head providing and receiving test signals through said probes, therein checking electrical properties of said semiconductor chips sequentially, said multiprobing semiconductor test method comprising the steps of:

determining a basic number of semiconductor chips to be tested simultaneously;

determining a number of semiconductor chips formed along each column of the semiconductor wafer;

determining a number of groups of semiconductor chips in each column for simultaneously testing by dividing the number of semiconductor chips in each column by the basic number of semiconductor ships to be tested simultaneously;

when the number of groups in adjacent columns is the same, a center position of groups in adjacent columns are arranged adjacently;

when the number of groups in adjacent columns is different, displacing a center position of one of the groups in the adjacent columns from a corresponding center position of a group in the other adjacent column by half the basic number, wherein groups at ends of a row of columns are not arranged in a straight line in a row direction with a group in the adjacent column;

providing as many probes as the basic number of semiconductor chips to be simultaneously tested at a center position of a first group;

providing said test head and testing said first group; and

sequentially moving to each center position of an adjacent group and testing until all the semiconductor chips on the wafer are tested.

4. A multiprobing semiconductor test method according to claim 3, wherein said step of displacing a center position, further comprising the step of determining a difference in the number of semiconductor chips between the groups at both ends of said column to be not greater than 1.