Matrix array of active matrix LCD and manufacturing method thereof
First Claim
1. A matrix array of an active matrix liquid crystal display comprising:
- an insulating substrate;
a gate line extending in a first direction on said substrate and having a first region corresponding to a gate electrode and a second region connected to and adjacent said first region, said first and second regions being separate portions of said gate line, and said gate line exposing a portion of said substrate;
a first insulating layer formed on said line and on said exposed portion of said substrate;
a first semiconductor layer formed above and in overlapping relation with said gate line;
a data line provided on said substrate and extending in a second direction crossing said second region of said gate line on said semiconductor layer and having a first protruding portion extending in said first direction above said first region of said gate line, and a second portion contiguous with said first portion, said second direction perpendicular to said first direction, said first and second portions being separate portions of said data line, and said first and second portions of said data line overlying said gate line;
a source electrode including said protruding portion of said data line;
a thin film transistor provided on said substrate including a drain electrode formed on the opposite side of said source electrode;
a pixel electrode coupled to said drain electrode and overlying said second region of said gate line; and
a storage capacitor including a portion of the second region of said gate line as a first storage capacitor electrode.
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Accused Products
Abstract
A matrix array of an active matrix liquid crystal display (AMLCD) and a manufacturing method thereof by which aperture ratio is enhanced by an optimum structure design of a line of the matrix array and a thin film transistor (TFT) so as to reduce power consumption, increase luminance, and lower reflection, thus improving contrast ratio. Aperture ratio is increased by forming the TFT above the gate line and providing non-linear TFT. The parasitic capacitor, occurring between the gate busline and the drain electrode, can be reduced when a TFT having the same channel length is manufactured due to effect of channel length extension. Therefore, level shifts of the pixel voltage can be reduced so that flicker is reduced and video quality is enhanced.
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Citations
26 Claims
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1. A matrix array of an active matrix liquid crystal display comprising:
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an insulating substrate; a gate line extending in a first direction on said substrate and having a first region corresponding to a gate electrode and a second region connected to and adjacent said first region, said first and second regions being separate portions of said gate line, and said gate line exposing a portion of said substrate; a first insulating layer formed on said line and on said exposed portion of said substrate; a first semiconductor layer formed above and in overlapping relation with said gate line; a data line provided on said substrate and extending in a second direction crossing said second region of said gate line on said semiconductor layer and having a first protruding portion extending in said first direction above said first region of said gate line, and a second portion contiguous with said first portion, said second direction perpendicular to said first direction, said first and second portions being separate portions of said data line, and said first and second portions of said data line overlying said gate line; a source electrode including said protruding portion of said data line; a thin film transistor provided on said substrate including a drain electrode formed on the opposite side of said source electrode; a pixel electrode coupled to said drain electrode and overlying said second region of said gate line; and a storage capacitor including a portion of the second region of said gate line as a first storage capacitor electrode. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A liquid crystal display comprising:
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a gate line extending in a first direction; a data line extending in a second direction different than said first direction, said second direction perpendicular to said first direction, and said data line having a protruding first portion extending in said first direction, and a second portion adjacent said first portion and extending in said second direction, wherein said first and second portions of said data line are contiguous and separate portions of said data line, and wherein said first and second portions overlying said gate line; a source electrode including said first portion of said data line; and a drain electrode spaced from said first and second portions of said data line and from said source electrode, wherein, upon application of a voltage to said gate line, a current flows from said first and second portions of said data line to said drain electrode. - View Dependent Claims (11, 12, 13, 14, 15, 16, 17)
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18. A liquid crystal display comprising:
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a gate line having a first portion extending in a first direction and a second portion extending in a second direction different than said first direction; a data line extending in said second direction, said data line having a protruding first portion extending in said first direction, and a second portion adjacent said first portion and extending in said second direction, said first portion of said data line overlying said first portion of said gate line, and said second portion of said data line overlying said second portion of said gate line; a source electrode including said first portion of said data line; and a drain electrode spaced from said first and second portions of said data line and from said source electrode, wherein, upon application of a voltage to said gate line, a current flows from said first and second portions of said data line to said drain electrode. - View Dependent Claims (19, 20, 21)
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22. A method of fabricating a liquid crystal display device comprising the steps of:
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providing a first conductive layer on a surface of a substrate; patterning said first conductive layer on said surface of said substrate, said patterned first conductive layer exposing a portion of said surface of said substrate, and extending in a first direction on said surface of said substrate; forming an insulative layer on said first conductive layer and said exposed portion of said surface of said substrate; forming a semiconductor layer on said insulative layer, said semiconductor layer having an amorphous silicon layer and a doped amorphous silicon layer; patterning said semiconductor layer to overlap said portion of said surface of said substrate and said first conductive layer; forming a second conductive layer on said substrate; and patterning said second conductive layer to form; a data line over a portion of said semiconductor layer overlying said first conductive layer, and extending in a second direction different than said first direction, said data line having a protruding portion over said portion of said semiconductor layer overlying said first conductive layer and extending in said first direction; and a source electrode overlying said exposed portion of said surface of said substrate, said source electrode being spaced from said protruding portion and a part of said data line contiguous with said protruding portion such that upon application of a voltage to said data line contiguous with protruding portion and from said protruding portion to said source electrode. - View Dependent Claims (23, 24, 25, 26)
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Specification