Timing system for mobile cellular radio receivers

• US 5,694,392 A
• Filed: 10/30/1995
• Issued: 12/02/1997
• Est. Priority Date: 10/30/1995
• Status: Expired due to Fees

• Current Assignee: VLSI Technology, Inc. (Koninklijke Philips N.V.)
• Original Assignee: VLSI Technology, Inc. (Koninklijke Philips N.V.)
• Inventors: Bocaert, Bruno, Whittle, John, Gaglione, Philippe
• Primary Examiner(s): Safourek, Benedict V.
• Assistant Examiner(s): NGO, RICKY QUOC
• Application Number:
  US08/550,433
• Time in Patent Office: 764 Days
• Field of Search: 455/49.1, 455/50.1, 455/67.1, 455/67.6, 455/54.1, 375/354, 375/355, 375/316, 370/313, 370/337, 370/347, 370/503, 370/516, 370/517, 370/518
• US Class Current: 370/337
• CPC Class Codes: H04B 7/2684 Synchronisation of a mobile station with more than one base station
• CPC Class Codes: H04W 56/0035 detecting errors in frequency or phase

Abstract

A hardware timing system for a cellular telephone comprises a master counter and a slave counter. The slave counter controls timing window generators in synchronism with the time frame of the local base station. The phases of timing frames of other base stations are monitored using the master counter.

Claims

1. A timing system for a mobile receiver of a cellular communication network wherein base stations communicate with mobile receivers by means of a time division multiple access protocol defined in a repetitive time frame, the phase of the time frame being different for different ones of the base stations, said system comprising:

means for providing a system clock signal;

a master cyclic counter for counting said system clock and defining a counting cycle corresponding to said time frame;

a slave counter for counting said system clock;

a first comparator for comparing a first set count value with a count from said slave counter to provide a starting signal;

a second comparator for comparing a second set count value with a count value from said slave counter to provide a terminating signal;

means for determining a first master count value of said master counter in response to an event having a predetermined position within said time frame;

means for providing a second master count value in accordance with said first master count value and said predetermined position; and

a third comparator for comparing a count of said master counter with said second master count value to reset said slave counter.

2. A timing system according to claim 1 wherein said means for determining said first master count value comprises a latch responsive to said event.

3. A timing system according to claim 1 wherein said means for providing said second master count value includes a storage register.

4. A timing system according to claim 1 and further comprising a timing window generator responsive to said starting signal and said terminating signal.

5. A timing system according to claim 1 and further comprising a fourth comparator for comparing a count in said master counter with a selectable count to generate an interrupt signal for a microprocessor.

6. A timing system for use in a time division multiple access communication system, said timing system comprising:

means for providing a system clock signal;

a master cyclic counter for counting said system clock and defining a counting cycle;

a slave counter for counting said system clock;

a plurality of timing window generating means each timing window generating means including means for comparing a first respective set count value with a count from said slave counter to provide a starting signal and means for comparing a second respective set count value with a count value from said slave counter to provide a terminating signal;

means for determining a first master count value of said master counter in response to a control signal;

means for providing a second master count value; and

a comparator for comparing a count of said master counter with said second master count value to reset said slave counter.

7. A timing system according to claim 6 wherein said means for determining said first master count value comprises a latch responsive to control signal.

8. A timing system according to claim 6 wherein said means for providing said second master count value includes a storage register.

9. A timing system according to claim 6 and further comprising a second comparator for comparing a count in said master counter with a selectable count to generate an interrupt signal for a microprocessor.

10. A timing system comprising:

means for providing a system clock signal;

a master cyclic counter for counting said system clock and defining a counting cycle;

a slave counter for counting said system clock;

at least one timing window generating means each timing window generating means including means for comparing a first respective set count value with a count from said slave counter to provide a starting signal and means for comparing a second respective set count value with a count value from said slave counter to provide a terminating signal;

means for determining a first master count value of said master counter in response to a control signal;

means for providing a second master count value;

a comparator for comparing a count of said master counter with said second master count value to reset said slave counter; and

a second comparator for comparing a count in said master counter with a selectable count to generate an interrupt signal for a microprocessor.