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System and method for locating solder bumps on semiconductor chips or chip carriers

  • US 5,694,482 A
  • Filed: 01/06/1997
  • Issued: 12/02/1997
  • Est. Priority Date: 11/08/1994
  • Status: Expired due to Fees
First Claim
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1. A pattern recognition system comprising:

  • means for generating at least one reference pattern with a defined nominal location formed of individual features, wherein a minimum distance between any adjacent two individual features is defined as PMIN within a number of individual non-colinear features greater than two,means for storing a representation of said at least one reference pattern;

    means for capturing an image of an actual pattern to obtain a representation of an imaged pattern; and

    means for comparing said representation of said imaged pattern with said representation of said at least one reference pattern; and

    means for identifying a deviation of said imaged pattern from said reference pattern, said deviation being determined even if the individual features in said imaged pattern have been translated by more than one half PMIN.

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