Data processing system including buffering mechanism for inbound and outbound reads and posted writes

• US 5,694,556 A
• Filed: 06/07/1995
• Issued: 12/02/1997
• Est. Priority Date: 06/07/1995
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Thurber, Steven M., Neal, Dan M., Silha, Edward J.
• Primary Examiner(s): AUVE, GLENN ALLEN
• Application Number:
  US08/472,603
• Time in Patent Office: 909 Days
• Field of Search: 395/306, 395/308, 395/309, 395/293, 395/872
• US Class Current: 710/310
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence

Abstract

A data processing system includes a host processor, a number of peripheral devices, and one or more bridges which may connect between the host, peripheral devices and other hosts or peripheral devices such as in a network. Each bus to bus bridge connects between a primary bus and a secondary bus wherein for the purpose of clarity, the primary bus will be considered as the source for outbound transactions and the destination for inbound transactions and the secondary bus would be considered the destination for outbound transactions and the source for inbound transactions. Each bus to bus bridge includes an outbound data path, an inbound data path, and a control mechanism. The outbound data path includes a queued buffer for storing transactions in order of receipt from the primary bus where the requests in the queued buffer may be mixed as between read requests and write transactions, the outbound path also includes a number of parallel buffers for storing read reply data and address information. The inbound path is a minor image of the outbound path with read requests and write requests being stored in a sequential buffer and read replies being stored in a number of parallel buffers. Both the inbound path and the outbound path in the bus to bus bridge are controlled by a state machine which takes into consideration activity in both directions and permits or inhibits bypass transactions.

Claims

1. A data processing system, comprising:

one or more processors;

one or more peripheral devices;

a plurality of buses connecting said one or more processors and said one or more peripheral devices through one or more bridges; and

one or more bridges for controlling transactions between a first bus and a second bus of said plurality of buses, each said bridge comprising;

a first data path for handling transactions from said first bus to said second bus;

a second data path for handling transactions from said second bus to said first bus;

a controller for controlling gating and sequence of transactions between said first bus and said second bus through said first data path and said second data path;

wherein said controller further comprises a state machine for controlling transactions through said first data path and said second data path;

wherein said state machine controls gating of transactions in said first and second data paths in accordance with a predetermined logic structure; and

wherein said predetermined logic structure further comprises means for controlling read transactions and write transactions to eliminate flushing write buffers prior to read transactions being gated through said controller.

2. A data processing system according to claim 1, wherein said first data path and said second data path each further comprise:

a transaction router circuit connected to an input to said bridge for gating transactions to buffers in said data path;

one or more buffers connected to said transaction router circuit for storing read reply transactions;

two or more buffers connected to said transaction router circuit for storing read request transactions and write transactions;

a transaction selection circuit connected to outputs of said buffers for selecting one or more transactions to be outputted from said data path under the control of said controller.

3. A data processing system according to claim 1 wherein said first data path is an outbound data path.

4. A data processing system according to claim 1 wherein said second data path is an inbound data path.

5. The data processing system, as recited in claim 1, wherein said state machine includes means for allowing predetermined subsequent transaction types to be gated through said data paths ahead of predetermined previous transaction types in accordance with said predetermined logic structure.

6. The data processing system, as recited in claim 1, wherein said state machine includes means for preventing predetermined subsequent transaction types from being gated through said data paths ahead of predetermined previous transaction types in accordance with said predetermined logic structure.

7. A method for controlling a plurality of transactions from a first bus to a second bus through a bridge, in a data processing system comprising one or more processors, one or more peripheral devices, a plurality of busses connecting the one or more processors and the one or more peripheral devices through one or more bridges, and one or more bridges for controlling transactions between the first bus and the second bus of the plurality of busses, said method comprising the steps of:

providing a first data path for handling transactions from the first bus to the second bus;

providing a second data path for handling transactions from the second bus to the first bus;

providing a controller for controlling gating and sequence of transactions between the first bus and the second bus through the first data path and the second data path; and

controlling, by the controller, read transactions and write transactions through the first and second data paths in accordance with a predetermined logic structure to eliminate flushing write buffers prior to read transactions being gated through the data paths.

8. The method, as recited in claim 7, further including the step of allowing predetermined subsequent transaction types to be gated through said data paths ahead of predetermined previous transaction types in accordance with said predetermined logic structure.

9. The method, as recited in claim 7, further including the step of preventing predetermined subsequent transaction types from being gated through said data paths ahead of predetermined previous transaction types in accordance with said predetermined logic structure.

10. A data processing system, comprising:

one or more processors;

one or more peripheral devices;

a plurality of buses connecting said one or more processors and said one or more peripheral devices through one or more bridges;

one or more bridges for controlling transactions between a first bus and a second bus of said plurality of buses, each said bridge comprising;

a plurality of data paths for handling transactions between said first and second buses;

buffer means for storing write transactions and for storing read transactions, with multiple read and write transactions being allowed to reside in said bridge at the same time; and

a controller for controlling gating and sequence of said read and write transactions between said first and said second bus through said data paths without first flushing said write transactions from said buffer means.

11. A bus-to-bus bridge, comprising:

a plurality of data paths for handling transactions between a first bus and a second bus;

buffer means for storing write transactions and for storing read transactions, with multiple read and write transactions being allowed to reside in said bridge at the same time; and

a controller for controlling gating and sequence of said read and write transactions between said first bus and said second bus through said data paths without first flushing said write transactions from said buffer means.

12. A method for controlling a plurality of transactions between a first bus and a second bus through a bridge, said method comprising the steps of:

providing a plurality of data paths in the bridge for handling transactions between said first and second buses;

storing write transactions in a plurality of buffers in the bridge;

storing read transactions in said plurality of buffers, with multiple read and write transactions being allowed to reside in said bridge at the same time; and

controlling gating and sequence of said read and write transactions between said first and second buses through said data paths without first flushing said write transactions from said buffers.