Apparatus and method for synchronizing data transfers in a single instruction multiple data processor

• US 5,694,588 A
• Filed: 03/14/1995
• Issued: 12/02/1997
• Est. Priority Date: 05/07/1993
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Miyaguchi, Hiroshi, Ohara, Kazuhiro
• Primary Examiner(s): Eng, David Y.
• Application Number:
  US08/403,541
• Time in Patent Office: 994 Days
• Field of Search: 395/775, 395/800, 395/566, 395/733, 395/551, 395/821
• US Class Current: 712/225
• CPC Class Codes: G06F 15/8015 One dimensional arrays, e.g. rings, linear arrays, buses
• CPC Class Codes: G06F 9/3824 Operand accessing
• CPC Class Codes: G06F 9/3869 Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking

Abstract

A synchronous vector processor (SVP) device (102) has a plurality of processing elements (150) which are comprised of an RF1 register (166), an ALU (164) and an RF0 (158). The processing elements are operable to be disposed between the data input register DIR (154) and the data output register (DOR) (168) to process data therebetween. Data is received in DIR (154), transferred to the processing elements (150), processed and then output to the DOR (168). A fast response clock operates the DIR (154) such that the jitter on the input signal is tracked. The Read clock on the DOR (168) is a stable clock. Data transferred between the DIR (154) and the DOR (168) is buffered in an elastic buffer to provide a time based compensation (TBC). To facilitate this, a buffer is implemented in either the RF1 (168) or the RF0 (158). A dual global rotation pointer is provided to generate two pointers that are asynchronous. The first pointer allows data to be transferred to the buffered area from/to the ALU (164) and the second pointer allows data to be transferred to the DOR (168) from the RF0 (158) or from a DIR (154) to the RF1 (166). A hardware interrupt is provided to perform this asynchronous transfer.

Claims

1. A processing system for receiving input data, processing the received input data and outputting processed data, comprising:

a data input register for receiving and storing the input data, said input register having a serial input port and a first parallel data port, such that the data is received via said serial input port in a serial manner in response to a write clock and stored so as to be accessible via said first parallel port in a parallel manner in response to a processor clock;

a processor for processing data in accordance with a predetermined processing algorithm to form processed data, said processor being connected to said first parallel port so that input data can be transferred from said data input register to said processor using said processor clock for processing thereof by said predetermined processing algorithm;

a data output register connected to said processor for receiving and storing said processed data from said processor using said processor clock, said output register having a second parallel data port and a serial output port, such that processed data can be transferred from said processor to said output register via said parallel port in a parallel manner and stored so as to be accessible for output via said serial output port in a serial manner in response to a read clock;

a first sync circuit for synchronizing the operation of said data input register to the operation of an external device connected to said input register by forming said write clock, said first sync circuit being responsive to and synchronized with said input data;

a second sync circuit for synchronizing the operation of said data output register with the operation of an external device connected to said output register by forming said read clock, said second sync circuit being separate and independent of said first sync circuit, said processor clock operating asynchronously from at least one of said read clock and said write clock; and

an interrupt circuit being responsive to said first sync circuit and said second sync circuit for interrupting the processing operation of said processor, thereby initiating an interruptive transfer of data between said processor and at least one of said input and output registers.

2. The processing system of claim 1, wherein said interrupt circuit is responsive to only one of said first and second sync circuits for interrupting the processing operation of said processor to initiate the transfer of data between said processor and only one of said input and output registers, and said processor being synchronized to the one of said first and second sync circuits associated with the other of said input and output registers.

3. The processing system of claim 1, wherein:

said first sync circuit is operable to track jitter in the input data; and

said second sync circuit is referenced to an external clock reference that is more stable than the operation of said first sync circuit.

4. The processing system of claim 3, further comprising an elastic buffer connected to either said first parallel port of said input register or to said second parallel port of said output register so that data can be exchanged among said input or output register, as the case may be, said processor, and said elastic buffer;

and

said elastic buffer having associated first and second pointers, said first pointer operational to specify a location in said elastic buffer for transfer of said data between said elastic buffer and said processor, said second pointer operational to specify a location in said elastic buffer for transfer of said data between said input or output register and said elastic buffer.

5. The processing system of claim 1, wherein said processor comprises:

a first register file connected to said first parallel port of said input register for receiving and storing data from said data input register;

a second register file connected to said parallel port of said output register for receiving and storing said processed data from said processor for transfer to said data output register;

an arithmetic logic unit for processing data in accordance with said predetermined processing algorithm to generate said processed data, said arithmetic logic unit connected to said first and second register files, said arithmetic logic unit interfacing with said first and second register files during said processing operation;

working registers for utilization by said arithmetic logic unit during processing thereof to store processing parameters and intermediate processing data therein during said processing operation; and

wherein

the contents of said working registers are saved in response to an interrupt from said interrupt circuit until said interruptive transfer is completed.

6. The processing system of claim 5, wherein:

said first sync circuit is operable to track jitter on the input data;

said second sync circuit is referenced to an external clock reference that is relatively stable compared to the operation of said first sync circuit; and

further comprising;

an elastic buffer associated with one of said first and second register files, so that data can be exchanged among said input or output register, as the case may be, said processor, and said elastic buffer; and

said elastic buffer having associated first and second pointers, said first pointer operational to specify a location in said elastic buffer for transfer of said data between said elastic buffer and said processor, said second pointer operational to specify a location in said elastic buffer for transfer of said data between said input or output register and said elastic buffer.

7. The processing system of claim 6, wherein said interrupt circuit is responsive to only one of said first and second sync circuits for interrupting the processing operation of said processor to initiate the transfer of data between said processor and only one of said input and output registers, and said processor being synchronized to the one of said first and second sync circuits associated with the other of said input and output registers.

8. A processing system for receiving input data words, processing a plurality of the received data words in parallel and outputting processed data, comprising:

a data input register for receiving and storing the input data words, said input register having a serial input port and a first parallel data port, such that the data words are received via said serial input port in a serial manner in response to a write clock and stored so as to be accessible via said first parallel port in a parallel manner in response to a processor clock;

a plurality of processing elements, each for processing one of said data words in accordance with a predetermined processing algorithm to form processed data, said plurality of processing elements being connected to said first parallel port so that a different one of said input data words can be transferred from said data input register to each one of said plurality of processing elements using said processor clock for processing thereof by said predetermined processing algorithm;

a data output register connected to each of said processing elements for receiving and storing said processed data from each of said processing elements using said processor clock, said output register having a second parallel data port and a serial output port, such that processed data can be transferred from said processing elements to said output register via said parallel port in a parallel manner and stored so as to be accessible for output via said serial output port in a serial manner in response to a read clock;

a first sync circuit for synchronizing the operation of said data input register to the operation of an external device connected to said input register by forming said write clock, said first sync circuit being responsive to and synchronized with said input data;

a second sync circuit for synchronizing the operation of said data output register with the operation of an external device connected to said output register by forming said read clock, said second sync circuit being separate and independent of said first sync circuit, said processor clock operating asynchronously from at least one of said read clock and said write clock; and

an interrupt circuit being responsive to said first sync circuit and said second sync circuit for interrupting the processing operation of said processing element, thereby initiating an interruptive transfer of data between said processing element and at least one of said input and output registers.

9. The processing system of claim 8, wherein said interrupt circuit is responsive to only one of said first and second sync circuits for interrupting the processing operation of each of said processing elements to initiate the transfer of data between said processing elements and only one of said input and output registers, and each of said processing elements being synchronized to the one of said first and second synch circuits associated with the other of said input and output registers.

10. The processing system of claim 8, wherein:

said first sync circuit is operable to track jitter in the input data; and

said second sync circuit is referenced to an external clock reference that is more stable than the operation of said first sync circuit.

11. The processing system of claim 10, further comprising an elastic buffer connected to either said first parallel port of said input register or to said second parallel port of said output register so that data can be exchanged among said input or output register, as the case may be, said processor, and said elastic buffer;

and

said elastic buffer having associated first and second pointers, said first pointer operational to specify a location in said elastic buffer for transfer of said data between said elastic buffer and said processor, said second pointer operational to specify a location in said elastic buffer for transfer of said data between said input or output register and said elastic buffer.

12. The processing system of claim 8, wherein said processing element comprises:

a first register file connected to said first parallel port of said input register for receiving and storing data from said data input register;

a second register file connected to said parallel port of said output register for receiving and storing said processed data from said processing element for transfer to said data output register;

an arithmetic logic unit for processing data in accordance with said predetermined processing algorithm to generate said processed data, said arithmetic logic unit connected to said first and second register files, said arithmetic logic unit interfacing with said first and second register files during said processing operation;

working registers for utilization by said arithmetic logic unit during processing thereof to store processing parameters and intermediate processing data therein during said processing operation; and

wherein

the contents of said working registers are saved in response to an interrupt from said interrupt circuit until said interruptive transfer is completed.

13. The processing system of claim 12, wherein:

said first sync circuit is operable to track jitter on the input data;

said second sync circuit is referenced to an external clock reference that is relatively stable compared to the operation of said first sync circuit; and

further comprising;

an elastic buffer associated with one of said first and second register files, so that data can be exchanged among said input or output register, as the case may be, said processor, and said elastic buffer; and

said elastic buffer having associated first and second pointers, said first pointer operational to specify a location in said elastic buffer for transfer of said data between said elastic buffer and said processor, said second pointer operational to specify a location in said elastic buffer for transfer of said data between said input or output register and said elastic buffer.

14. The processing system of claim 13, wherein said interrupt circuit is responsive to only one of said first and second sync circuits for interrupting the processing operation of each of said processing elements to initiate the transfer of data between each of said processing elements and only one of said input and output registers, and each of said processing elements being synchronized to the one of said first and second sync circuits associated with the other of said input and output registers.

15. A method for processing input data, comprising the steps of:

receiving and storing input data in a data input register in a serial manner using a write clock;

providing a processor;

transferring data in parallel from the input data register to the processor for processing in a first transfer step using a processor clock;

processing the data with the processor in accordance with a predetermined processing algorithm to form processed data therefrom;

transferring the processed data output by the processor in a second transfer step to a data output register using said processor clock for storage therein;

outputting the processed data therefrom in a serial manner using a read clock;

generating a first sync signal in synchronism with an external device connected to said input register and synchronizing said write clock and the operation of the receiving stop to the first sync signal;

independently generating a second sync signal in synchronism with an external device connected to said output register and synchronizing said read clock and the operation of the outputting step to the second sync signal, the first sync signal and the second sync signal operating asynchronously, wherein said processor clock operates asynchronously from at least one of said read clock and said write clock; and

interrupting the processing operation of the processor in response to at least one of said first and second sync signals to initiate at least one of the first and second transfer steps.

16. The method of claim 15, wherein the step of interrupting is operable to interrupt the processing operation of the processor to initiate only one of the first and second transfer steps, and further comprising synchronizing the step of processing to the one of the first and second sync signals associated with the other of the first and second transfer steps.

17. The method of claim 15, wherein:

the step of generating the first sync signal comprises generating a first sync signal and said write clock that tracks jitter in the input data; and

the step of generating the second sync signal comprises generating a second sync signal and said read clock that is referenced to an external clock reference that is more stable than the first sync signal.

18. The method of claim 15, further comprising:

providing an elastic buffer; and

wherein the first transfer step further includes;

transferring data into the elastic buffer from the input data register in accordance with a Write pointer that points to a predetermined location in the elastic buffer and transferring data from the elastic buffer to the processor in accordance with a Read pointer that points to another predetermined location in the elastic buffer.

19. The method of claim 15, further comprising:

providing an elastic buffer; and

wherein the second transfer step further includes;

transferring data into the elastic buffer from the processor in accordance with a Write pointer that points to a predetermined location in the elastic buffer and transferring data from the elastic buffer to the data output register in accordance with a Read pointer that points to another predetermined location in the elastic buffer.

20. The method of claim 15, wherein the step of providing a processor comprises:

providing a plurality of parallel processor elements, each processor element having a first register file, a second register file, an arithmetical logic unit interfaced with the first and second register files, and a working register file;

utilizing the working register file during the operation of the arithmetic logic unit to store processing parameters and intermediate processing data therein;

disposing the processor elements between the data input register and the data output register;

the first step of transferring data in parallel from the input data register to the processor comprises transferring and storing data from the data input register to the first register file;

the step of processing comprises interfacing the arithmetic logic unit with the first register file and processing data therein in accordance with the predetermined processing algorithm to generate the processed data and operating the arithmetic logic unit in conjunction with the first and second transfer steps; and

outputting the processed data and storing it in the second register file for transfer from the second register file to the data output register via the second transfer step; and

the step of interrupting the processor operation further includes saving the contents of the working register until the first or second transfer step, as the case may be, associated therewith is complete.

21. The method of claim 19, wherein:

the first sync signal is operable to track jitter on the input data;

the second sync signal is referenced to an external clock reference that is relatively stable compared to the first sync signal, and further comprising;

providing an elastic buffer and associating the elastic buffer with one of the first and second transfer steps;

transferring data into the elastic buffer associated with the first or second transfer step in accordance with a Write pointer that points to a predetermined location in the elastic buffer and outputting data in accordance with a Read pointer that points to another predetermined location in the elastic buffer;

synchronizing the operation of the Write pointer with one of the first and second sync signals; and

synchronizing the Read pointer with the other of the first and second sync signals.