Hardware arrangement of effectively expanding data processing time in pipelining in a microcomputer system and a method thereof

• US 5,694,613 A
• Filed: 09/24/1996
• Issued: 12/02/1997
• Est. Priority Date: 07/02/1993
• Status: Expired due to Term

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Suzuki, Kazumasa
• Primary Examiner(s): Geckil, Mehmet B.
• Application Number:
  US08/719,241
• Time in Patent Office: 434 Days
• Field of Search: 395/800, 395/375, 395/775, 395/298, 395/183.1, 395/733, 395/500
• US Class Current: 712/231
• CPC Class Codes: G06F 9/3861 Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00
• CPC Class Codes: G06F 9/3867 using instruction pipelines
• CPC Class Codes: G06F 9/3869 Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking

Abstract

A pipelined data processing arrangement which is subject to an instruction interrupt is disclosed. The pipelined arrangment is provided with a plurality of stages each of which has a temporary storage. In order to increase an actual time for executing instructions in the pipelined arrangement, the temporary storages which exhibit large delay are replaced by dynamic latches each having a smaller delay time without adversely affecting the operation of the pipelined arrangement.

Claims

1. A pipelined data processing arrangement having a plurality of stages which are coupled in series and each of which includes a temporary storage register, comprising:

a first stage for successively issuing a plurality of instructions in synchronism with time slots, said first stage including first storage means which, in response to occurrence of an interrupt request, retains therein an instruction applied thereto over one or more time slots which follow a time slot wherein said interrupt request has been issued;

a second stage coupled to decode each of said instructions applied thereto from said first stage, said second stage issuing said interrupt request if pipelined operation should be interrupted, said second stage including second storage means which holds a decoded instruction only during a time slot for which said decoded instruction is applied to thereto;

add

a third stage coupled to said second stage, said third stage including;

third storage means which, in response said interrupt request, retains therein a first instruction applied thereto from said second stage over one time slot which follows a time slot wherein said interrupt request has been issued, said first instruction being applied to said third storage means at a time slot wherein said interrupt request is issued; and

fourth storage means which, in response to said interrupt request, retains therein a second instruction applied thereto from said second stage over one time slot which follows two consecutive time slots wherein said interrupt request has been issued at the former time slot of said two cosecutive time slots, said second instruction being applied to said fourth storage means at a time slot immediately after said interrupt request is issued,

wherein said third storage means acquiring said second instruction stored in said fourth storage means at the latter time slot of said two consecutive time slots.

2. A pipelined data processing arrangement as claimed in claim 1, wherein said fourth storage means includes a delay for delaying said interrupt request by one time slot.

3. A pipelined data processing arrangement as claimed in claim 1, wherein said third stage further includes:

fifth storage means which, in response said interrupt request, retains therein a first data applied thereto from said second stage over one time slot which follows a time slot wherein said interrupt request has been issued, said first data being applied to said third storage means at a time slot wherein said interrupt request is issued; and

fifth storage means which, in response to said interrupt request, retains therein a second data applied thereto from said second stage over one time slot which follows two consecutive time slots wherein said interrupt request has been issued at the former time slot of said two cosecutive time slots, said second data being applied to said fifth storage means at a time slot immediately after said interrupt request is issued,

wherein said third storage means acquiring said second data stored in said fifth storage means at the latter time slot of said two consecutive time slots.

4. A method of reducing delay in data processing in a pipelined arrangement having a plurality of stages which are coupled in series, comprising the steps of:

(a) successively issuing a plurality of instructions in synchronism with time slots at a first stage;

(b) responding to occurrence of an interrupt request and retaining, at first storage means included in said first stage, an instruction applied thereto over one or more time slots which follow a time slot wherein said interrupt request has been issued;

(c) decoding each of said instructions at a second stage which, in addition to the instruction decoding, issues said interrupt request if pipelined operation should be interrupted;

(d) responding to said interrupt request and retaining, at second storage means included in said second stage, a decoded instruction over one or more time slots which follow said time slot wherein said interrupt request has been issued; and

(e) successively data processing at a plurality of data processing stages, coupled to said second stage, in a manner which holds, at dynamic latch means included in each of said data processing stages, a data processing instruction and data, both of which are applied from a previous stage, only during a time slot for which said data processing instruction is applied thereto.

5. A pipelined data processing arrangement having a plurality of stages which are coupled in series, comprising:

a first stage for successively issuing a plurality of instructions in synchronism with time slots, said first stage including storage means which, in response to occurrence of an interrupt request, retains therein an instruction applied thereto over one or more time slots which follow a time slot wherein said interrupt request has been issued;

a second stage coupled to decode each of said instructions applied thereto from said first stage, said second stage issuing said interrupt request if pipelined operation should be interrupted, said second stage including dynamic latch means for holding a decoded instruction only during a time slot wherein said decoded instruction has been issued; and

a third stage coupled to said second stage, said third stage including;

first storage means which, in response to said interrupt request, retains therein a data processing instruction and data, both of which are applied thereto from said second stage, over one time slot which follows a time slot wherein said interrupt request has been issued; and

second storage means which, in response to said interrupt request, retains therein a data processing instruction and data, both of which respectively follow said data processing instruction and said data both retained in said first storage means, over one time slot which follows two consecutive time slots at a first time slot of which said interrupt request has been issued.

6. A pipelined data processing arrangement as claimed in claim 5, wherein said second storage means includes two delay means for respectively delaying said data processing instruction and said data, both of which are to be retained in said second storage means, by one time slot.

7. A pipelined data processing arrangement as claimed in claim 5, said first storage means stores said data processing instruction and said data, both of which have retained in said second storage means, over a second time slot of said two consecutive time slots.

8. A pipelined data processing arrangement as claimed in claim 5, further including a plurality of data processing stages which follow said third stage, each of said data processing stages including dynamic latch means for holding a data processing instruction and data, both of which are applied from a previous stage, only during a time slot for which said data processing instruction is applied thereto.

9. A method of reducing delay in data processing in a pipelined arrangement having a plurality of stages which are coupled in series, comprising the steps of:

(a) successively issuing a plurality of instructions in synchronism with time slots at a first stage;

(b) responding to occurrence of an interrupt request and retaining, at first storage means included in said first stage, an instruction applied thereto over one or more time slots which follow a time slot wherein said interrupt request has been issued;

(c) decoding each of said instructions at a second stage which, in addition to the instruction decoding, issues said interrupt request if pipelined operation should be interrupted;

(d) responding to said interrupt request and retaining, at dynamic latch means included in said second stage, a decoded instruction only during a time slot wherein said decoded instruction has been issued;

(e) responding to said interrupt request and retaining, at second storage means included in a third stage, a data processing instruction and data, both of which are applied to said second storage means from said second stage, over one time slot which follows a time slot wherein said interrupt request has been issued; and

(f) responding to said interrupt request and retaining, at third storage means included in said third stage, a data processing instruction and data, both of which respectively follow said data processing instruction and said data both retained in said second storage means, over one time slot which follows two consecutive time slots at a first time slot of which said interrupt request has been issued.

10. A method as claimed in claim 9, wherein step (f) includes:

storing said data processing instruction and said data, both of which have been retained in said third storage means, over a second time slot of said two consecutive time slots.

11. A method as claimed in claim 9, further including the step of:

(g) successively performing data processing at a plurality of data processing stages, coupled to said second stage, in a manner which holds, at dynamic latch means included in each of said data processing stages, a data processing instruction and data, both of which are applied from a previous stage, only during a time slot for which said data processing instruction is applied thereto.