Fabrication method of semiconductor memory device containing CMOS transistors

• US 5,696,012 A
• Filed: 12/24/1996
• Issued: 12/09/1997
• Est. Priority Date: 12/29/1995
• Status: Expired due to Term

• Current Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Original Assignee: LG Semico Company Limited (SK Hynix Inc.)
• Inventors: Son, Jeong-Hwan
• Primary Examiner(s): Niebling, John
• Assistant Examiner(s): Booth, Richard A.
• Application Number:
  US08/772,851
• Time in Patent Office: 350 Days
• Field of Search: 437/57, 437/34, 437/44, 437/40-41
• US Class Current: 438/231
• CPC Class Codes: H01L 21/823864 with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape

Abstract

A fabrication method for a semiconductor memory device which remarkably improves a short-channel characteristic, and increases a driving electric current of the device by differently forming the thickness of side wall spacers formed at the sides of polysilicon gates in nMOS and pMOS regions, includes forming a gate insulating film on a semiconductor substrate having first and second regions, forming first and second gate electrodes in the first and second regions, respectively, on the substrate, forming a first conductive low concentration impurity area at the sides of the first gate electrode, forming a second conductive low concentration impurity area at the sides of the second gate electrode, forming a first insulating film on the substrate and a second insulating film on the first insulating film, stripping the second insulating film in the first region, forming first sidewall spacers at the sides of the first gate electrode, forming a first conductive high concentration impurity area in the substrate at the sides of the first gate electrode, forming second sidewall spacers composed of the first and second insulating films at the sides of the second gate electrode in the second region, and forming a second conductive high concentration impurity area in the substrate at the sides of the second gate electrode.

Claims

1. A fabrication method for a semiconductor memory device, comprising:

forming a gate insulating film on a semiconductor substrate having first and second regions;

forming first and second gate electrodes in the first and second regions, respectively, on the substrate;

forming a first conductive low concentration impurity area in the substrate of the first region at the sides of the first gate electrode;

forming a second conductive low concentration impurity region in the second region on the substrate at the sides of the second gate electrode;

forming a first insulating film on the substrate having the first and second gate electrodes thereon and a second insulating film on the first insulating film;

stripping the second insulating film in the first region;

forming first sidewall spacers at the sides of the first gate electrode by performing an anisotropic etching on the first insulating film in the first region;

forming a first conductive high concentration impurity area in the first region of the subtrate at the sides of the first gate electrode having the first sidewall spacers;

forming second sidewall spacers composed of the first and second insulating films at the sides of the second gate electrode by performing an anisotropic etching on the first and second insulating films in the second region; and

forming a second conductive high concentration impurity region in the substrate of the second region at the sides of the second gate electrode having the second sidewall spacers.

2. The fabrication method of claim 1, wherein the first insulating film is composed of an oxide film, and the second insulating film is composed of a nitride film.

3. The fabrication method of claim 1, wherein the first insulating film is composed of a nitride film, and the second insulating film is composed of an oxide film.

4. The fabrication method of claim 1, wherein the first conductive impurity is an n-type impurity, and the second conductive impurity is a p-type impurity.

5. The fabrication method of claim 1, wherein the steps for forming the first sidewall spacers comprise:

forming the first insulating film;

forming a photoresist film on the second insulating film after forming the second insulating film on the first insulating film;

stripping the photoresist film in the first region; and

performing an anisotropic etching on the second insulating film, using the photoresist film as a mask.

6. The fabrication method of claim 1, wherein the steps for forming the second side wall spacers comprise:

forming a photoresist film on the second insulating film in the first and second regions;

forming sidewall spacers composed of the second insulating film on the first insulating film at the sides of the second gate electrode by performing an anisotropic etching on the second insulating film, using the photoresist film as a mask; and

forming sidewall spacers composed of the first insulating film between the sides of the second gate electrode and the sidewall spacers composed of the second insulating film by etching the first insulating film, using as a mask the photoresist film and the second insulating film.