Integrated circuit device

• US 5,696,402 A
• Filed: 05/22/1995
• Issued: 12/09/1997
• Est. Priority Date: 09/28/1965
• Status: Expired due to Fees

• Current Assignee: LI Second Family Limited Partnership
• Original Assignee: Chou H. Li
• Inventors: Li, Chou H.
• Primary Examiner(s): CARROLL, JAMES J
• Application Number:
  US08/446,423
• Time in Patent Office: 932 Days
• Field of Search: 256/662.1, 256/647.1, 257/499, 257/506, 257/509, 257/510, 257/622, 257/653
• US Class Current: 257/510
• CPC Class Codes: H01L 21/76232 of trenches having a shape other than rectangular or V-shape, e.g. rounded corners, oblique or rounded trench walls H01L21/76229 takes precedence
• CPC Class Codes: H01L 21/763 Polycrystalline semiconductor regions H01L21/76264 takes precedence
• CPC Class Codes: H01L 29/0657 characterised by the shape of the body

Abstract

An integrated circuit device comprising: a body of a semiconductor material having an upper surface and a bottom major surface; wall means defining in said semiconductor material body a microscopically precise depression or groove of a selected shape and size and extending for a selected length or depth from a selected position on said upper surface toward without reaching said bottom major surface; and a material chemically different from said semiconductor material and introduced into said semiconductor material through a selected portion of an exposed wall of! said groove to modify, in a predetermined manner, a selected electronic property of said semiconductor material the vicinity of said exposed wall.

Claims

1. An integrated circuit device comprising:

a solid state material having a selected shape and comprising a substrate of a first solid material having an upper surface and a bottom major surface, and further comprising a pocket of a second solid material, said pocket having a side surface and a lower surface which makes electronic contact with a selected portion of said upper surface of said substrate;

said materials of said substrate and of said pocket being so selected as to form, where said lower surface of said pocket makes electronic contact with said selected portion of said upper surface of said substrate, an electronic interfacial barrier which is substantially conductive under an applied bias of at least one selected polarity; and

wall means extending into said pocket to define a groove which adjoins at least said side surface of said pocket;

on a cross-section in a plane normally of said bottom surface of said substrate, said groove having a first curved portion which is in a vicinity of said barrier and has a first prespecified radius of curvature of less than one micron;

on a cross-section in a plane normally of said bottom major surface of said substrate, said groove having a second curved portion which has a second prespecified radius of curvature;

said second prespecified radius of curvature being significantly greater than said first prespecified radius of curvature but less than 1 cm.

2. An integrated circuit device comprising:

a solid state material having a selected shape and comprising a substrate of a first solid material having an upper surface and a bottom major surface, and further comprising a pocket of a second solid material, said pocket having a side surface and a lower surface which makes electronic contact with a selected portion of said upper surface of said substrate;

said materials of said substrate and of said pocket being so selected as to form, where said lower surface of said pocket makes electronic contact with said selected portion of said upper surface of said substrate, an electronic interfacial barrier which is substantially conductive under an applied bias of at least one selected polarity; and

wall means extending into said pocket to define a groove which adjoins at least said side surface of said pocket;

on a cross-section in a plane normally of said bottom surface of said substrate, said groove having a first curved portion which is in a vicinity of said barrier and has a first prespecified radius of curvature of less than one micron;

on a cross-section in a plane normally of said bottom major surface of said substrate, said groove having a second curved portion which has a second prespecified radius of curvature;

said second prespecified radius of curvature being at least twice greater than said first prespecified radius of curvature.

3. An integrated circuit device as in claim 2 in which said electronic interfacial barrier is a PN junction.

4. An integrated circuit device as in claim 3 in which said first curved portion is within 1 micron of a selected portion of said PN junction.

5. An integrated circuit device as in claim 4 in which said second curved portion is within 1 micron of said selected portion of said PN junction.

7. An integrated circuit device as in claim 2 in which said first curved portion is within 1 micron of a selected portion of said electronic interfacial barrier.

8. An integrated circuit device as in claim 7 in which said second curved portion is within 1 micron of said selected portion of said electronic interfacial barrier.

6. An integrated circuit device as in claim 6 in which said first curved portion is vertically spaced from said second curved portion.

9. An integrated circuit device comprising:

a solid state material having a selected shape and comprising a substrate of a first solid material having an upper surface and a bottom major surface, and further comprising a pocket of a second solid material, said pocket having a side surface and a lower surface which makes electronic contact with a selected portion of said upper surface of said substrate;

said materials of said substrate and of said pocket being so selected as to form, where said lower surface of said pocket makes electronic contact with said selected portion of said upper surface of said substrate, an electronic interfacial barrier which is substantially conductive under an applied bias of at least one selected polarity; and

wall means extending into said pocket to define a groove which adjoins at least said side surface of said pocket;

on a cross-section in a plane normally of said bottom surface of said substrate, said groove having a first curved portion which is in a vicinity of said barrier and has a first prespecified radius of curvature of less than one micron;

on a cross-section in a plane normally of said bottom major surface of said substrate, said groove having a second curved portion which has a second prespecified radius of curvature;

said second prespecified radius of curvature being 1-4 orders of magnitude greater than said first prespecified radius of curvature but less than 1 cm.

10. An integrated circuit device as in claim 9 in which said electronic interfacial barrier is a PN junction.

11. An integrated circuit device as in claim 10 in which said first curved portion is within 1 micron of a selected portion of said PN junction.

12. An integrated circuit device as in claim 11 in which said second curved portion is within 1 micron of said selected portion of said PN junction.

13. An integrated circuit device as in claim 12 in which said first curved portion is vertically spaced from said second curved portion.