Method and apparatus for autocalibrating the center frequency of a voltage controlled oscillator of a phase locked loop
First Claim
1. In a clock multiplier having a phase-locked loop including a phase-frequency detector and a voltage controlled oscillator wherein the voltage control oscillator outputs a signal having a frequency at some multiple of an input frequency received by the phase-frequency detector based upon a center frequency, an improvement directed to setting a center frequency of the voltage controlled oscillator, said improvement comprising:
- a frequency reference source means, connected to an input of the phase-frequency detector, for providing a frequency reference signal at a selected center frequency;
adjustment means, connected between the phase-frequency detector and a course tuning input of the voltage controlled oscillator, for generating a course tuning current;
a voltage reference source means, connected to a voltage input of the voltage controlled oscillator, for providing a voltage reference signal;
means within the voltage controlled oscillator for biasing an output frequency using the course tuning current until a stable output frequency is achieved based upon the reference frequency; and
means for disconnecting the frequency reference source from the input of the phase-frequency detector and the voltage reference signal from the input of the voltage controlled oscillator to allow an input clock signal received by the phase-frequency detector to be multiplied by the voltage controlled oscillator as biased by the course tuning current.
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Accused Products
Abstract
The clock multiplying phase locked loop includes components for selectively setting a center frequency of a voltage controlled oscillator (VCO) to bias the VCO for operation within a selected range of input frequencies. To this end, the VCO is configured to output a signal at a selected center frequency based upon a tuning current provided to the VCO. Initially, a voltage input of the VCO is set to a reference voltage and a feedback signal is generated. The feedback signal, perhaps divided by N, is input to a phase-frequency detector. The phase-frequency detector also receives a reference frequency signal having a frequency at the selected center frequency. The detector outputs an UP or DOWN signal indicating whether the feedback signal is greater or less than the reference frequency signal. A center frequency adjustment unit receives the UP or DOWN signals from the detector and adjusts the tuning current to modify the center frequency of the VCO to reduce any difference between the feedback frequency and the reference frequency received by the phase-frequency detector. The VCO, the detector and the adjustment unit, as well as other components, operate in a loop causing the center frequency of the VCO to be iteratively adjusted until the center frequency approximates the selected center frequency to a selected degree of resolution. At that point, the voltage reference signal is disconnected from the voltage input of the VCO and the frequency reference signal is disconnected from the input of the phase-frequency detector, thus allowing the clock multiplier to operate as a phase locked loop (PLL). The tuning current, however, continues to be applied to the VCO to maintain the center frequency of the VCO at the selected center frequency such that further operation of the VCO is biased to that center frequency. Method and apparatus embodiments of the invention are disclosed.
92 Citations
13 Claims
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1. In a clock multiplier having a phase-locked loop including a phase-frequency detector and a voltage controlled oscillator wherein the voltage control oscillator outputs a signal having a frequency at some multiple of an input frequency received by the phase-frequency detector based upon a center frequency, an improvement directed to setting a center frequency of the voltage controlled oscillator, said improvement comprising:
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a frequency reference source means, connected to an input of the phase-frequency detector, for providing a frequency reference signal at a selected center frequency; adjustment means, connected between the phase-frequency detector and a course tuning input of the voltage controlled oscillator, for generating a course tuning current; a voltage reference source means, connected to a voltage input of the voltage controlled oscillator, for providing a voltage reference signal; means within the voltage controlled oscillator for biasing an output frequency using the course tuning current until a stable output frequency is achieved based upon the reference frequency; and means for disconnecting the frequency reference source from the input of the phase-frequency detector and the voltage reference signal from the input of the voltage controlled oscillator to allow an input clock signal received by the phase-frequency detector to be multiplied by the voltage controlled oscillator as biased by the course tuning current. - View Dependent Claims (2, 3)
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4. A method for setting a voltage controlled oscillator to a selected center frequency for use within a clock multiplier containing the voltage controlled oscillator and phase-frequency detector configured within a feedback loop, said method comprising the steps of:
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applying a frequency reference signal to an input of the phase-frequency detector at the selected center frequency; applying a voltage reference signal to an input of the voltage controlled oscillator and generating a feedback frequency signal from the voltage controlled oscillator in response thereto; iteratively comparing the feedback frequency signal from the voltage controlled oscillator to the selected center frequency, generating a course tuning current signal for reducing a difference between the output frequency and the selected center frequency, and applying the course tuning current signal to the voltage controlled oscillator until the voltage controlled oscillator is biased to the selected center frequency; and disconnecting the voltage reference source from the voltage input of the voltage controlled oscillator and disconnecting the frequency reference signal from an input of phase-frequency detector and instead inputting a clock signal.
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5. A clock multiplying phase lock looped circuit comprising:
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a phase-frequency detector for receiving an input clock signal and a feedback clock signal and for outputting a signal representative of phase/frequency differences therebetween; a charge pump for receiving the output signal from the phase-frequency detector and for inputting or outputting an amount of charge in response thereto; a loop filter, including one or more capacitors, for maintaining an amount of charge in response to operation of the charge pump; a voltage controlled oscillator having a voltage input signal connected to an output of the loop filter for generating an output clock signal having a frequency representative of the input voltage signal but multiplied by a predetermined factor N, said voltage controlled oscillator also having a voltage reference signal input and a course tuning current input; a divide-by-N circuit interconnecting an output of the voltage controlled oscillator and the feedback input of the phase-frequency detector; a voltage reference source for providing a reference voltage to the voltage controlled oscillator and for selectively providing the reference voltage also to the input voltage input of the voltage controlled oscillator; a reference frequency source for selectively providing a reference frequency as an input frequency to the phase-frequency detector; and an adjustment unit, connected between the output of the phase-frequency detector and the course tuning current input of the voltage controlled oscillator, for generating a course tuning current signal selected to minimize differences between the frequency reference signal and the feedback frequency reference signal, said course tuning current maintaining a center frequency of the voltage controlled oscillator at approximately the reference frequency. - View Dependent Claims (6, 7, 8, 9, 10)
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11. A clock multiplier circuit comprising:
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a phase locked loop circuit including a phase-frequency detector and a voltage controlled oscillator; a frequency reference source, connected to an input of the phase-frequency detector, for providing a frequency reference signal at a selected center frequency; adjustment unit, connected between the phase-frequency detector and a course tuning input of the voltage controlled oscillator, for generating a course tuning current; a voltage reference source, connected to a voltage input of the voltage controlled oscillator, for providing a voltage reference signal; circuitry within the voltage controlled oscillator for biasing an output frequency using the course tuning current until a stable output frequency is achieved based upon the reference frequency; and switches for disconnecting the frequency reference source from the input of the phase-frequency detector and the voltage reference signal from the input of the voltage controlled oscillator to allow an input clock signal received by the phase-frequency detector to be multiplied by the voltage controlled oscillator as biased by the course tuning current. - View Dependent Claims (12, 13)
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Specification