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Time multiplexing pixel frame buffer video output

  • US 5,696,534 A
  • Filed: 03/21/1995
  • Issued: 12/09/1997
  • Est. Priority Date: 03/21/1995
  • Status: Expired due to Term
First Claim
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1. An apparatus for multiplexing pixel data from a frame buffer for use by a RAMDAC for display on a display device comprising:

  • a) interleaving format circuits for coupling to a frame buffer and receiving interleaved pixel data having the form n/m;

    1, where n is a number of whole pixels being transmitted and m is a fraction of the data which forms a whole pixel which is transmitted during a single clock cycle, where n>

    m>

    1;

    b) logic circuits coupled to the interleaving format circuits for processing predetermined portions of the received interleaved pixel data to produce serialized pixel data for processing by said RAMDAC,wherein said interleaving format circuits include circuits which undo the interleaving performed by said frame buffer and assemble said pixel data as received from said frame buffer into corresponding sets of pixel data.

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