Time multiplexing pixel frame buffer video output
First Claim
1. An apparatus for multiplexing pixel data from a frame buffer for use by a RAMDAC for display on a display device comprising:
- a) interleaving format circuits for coupling to a frame buffer and receiving interleaved pixel data having the form n/m;
1, where n is a number of whole pixels being transmitted and m is a fraction of the data which forms a whole pixel which is transmitted during a single clock cycle, where n>
m>
1;
b) logic circuits coupled to the interleaving format circuits for processing predetermined portions of the received interleaved pixel data to produce serialized pixel data for processing by said RAMDAC,wherein said interleaving format circuits include circuits which undo the interleaving performed by said frame buffer and assemble said pixel data as received from said frame buffer into corresponding sets of pixel data.
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Accused Products
Abstract
A method and for multiplexing pixel data from a frame buffer to a RAMDAC to reduce the number of pins required. For many graphics operations optimal performance is achieved by storing an entire 32-bit pixel in a single RAM chip. When displaying video data from a frame buffer, pixels must be read out serially from the frame buffer at real-time speeds. A frame buffer memory with 16 pins for serial video output is used. An entire 32-bit pixel is stored in a single RAM chip. For a 32-bit pixel containing four byte (8-bit) quantities designated X, B, G and R, on the first clock cycle, the X and B bytes are made available on the 16 pins of the frame buffer. On the next clock cycle, the G and R bytes are made available. Thus, over two cycles the entire 32-bit pixel is output from the frame buffer to a RAMDAC which samples the X and B bytes on 16 input pins. The RAMDAC stores these X and B bytes in an internal register. On the next clock cycle it samples the G and R bytes. The DAC then reassembles the X, B, G and R bytes into a single 32-bit pixel for conversion into video. In this manner, 32-bit pixels are communicated across a 16-bit pixel data bus.
16 Citations
20 Claims
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1. An apparatus for multiplexing pixel data from a frame buffer for use by a RAMDAC for display on a display device comprising:
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a) interleaving format circuits for coupling to a frame buffer and receiving interleaved pixel data having the form n/m;
1, where n is a number of whole pixels being transmitted and m is a fraction of the data which forms a whole pixel which is transmitted during a single clock cycle, where n>
m>
1;b) logic circuits coupled to the interleaving format circuits for processing predetermined portions of the received interleaved pixel data to produce serialized pixel data for processing by said RAMDAC, wherein said interleaving format circuits include circuits which undo the interleaving performed by said frame buffer and assemble said pixel data as received from said frame buffer into corresponding sets of pixel data. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
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18. A method for multiplexing pixel data from a frame buffer for use by a RAMDAC for display on a display device comprising the steps of:
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a) undoing the interleaving performed by said frame buffer and assembling said pixel data as received from said frame buffer into corresponding sets of pixel data, said pixel data having the form n/m;
1, where n is a number of whole pixels being transmitted and m is a fraction of the data which forms a whole pixel which is transmitted during a single clock cycle, where n>
m>
;b) processing predetermined portions of the received interleaved pixel data to produce serialized pixel data for processing by said RAMDAC, wherein said undoing and assembling produces a plurality of complete pixel sets, each formed by a predetermined number of bits. - View Dependent Claims (19, 20)
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Specification