3D imaging underwater laser radar

• US 5,696,577 A
• Filed: 06/06/1995
• Issued: 12/09/1997
• Est. Priority Date: 03/23/1992
• Status: Expired due to Term

• Current Assignee: Continental Autonomous Mobility US LLC (Continental AG)
• Original Assignee: Advanced Scientific Concepts, Inc.
• Inventors: Bailey, Howard W., Stettner, Roger
• Primary Examiner(s): Hellner, Mark
• Application Number:
  US08/467,216
• Time in Patent Office: 917 Days
• Field of Search: 250/332, 250/330, 250/339, 356/5.01, 356/4.01
• US Class Current: 356/4.01
• CPC Class Codes: G01S 17/894 3D imaging with simultaneous measurement of time-of-flight at a 2D array of receiver pixels, e.g. time-of-flight cameras or flash lidar
• CPC Class Codes: G01S 7/4863 Detector arrays, e.g. charge-transfer gates
• CPC Class Codes: G01T 1/28 with secondary-emission detectors

Abstract

A three dimensional imaging device and method is presented which uses a pulsed light source for detecting objects enveloped by a light-transmitting and light-reflecting and scattering medium such as water or biological tissues. By means of high-speed switching between many storage capacitors the third dimension is recorded by the device with a single pulse from the light-source. The device consists of the pulsed light source, optics for collecting the reflected and scattered light, one or more sensors for detecting the light, drive and output electronics for timing and signal conditioning of data generated by the sensors and processing electronics and software for converting the sensor data to a three dimensional image. The sensors use known technologies for light amplification but collect and process the light-amplified data in a unique manner, using an analog-processing readout chip. The readout chip is a two dimensional array of collectors or detectors combined in very close proximity with associated storage and switching electronics. The two dimensional array defines two dimensions of the image. The third dimension is associated with the time of return of the light pulse.

Claims

1. An analog-processing readout chip comprising

a plurality of means for collecting or detecting signal data and

readout electronics comprising

a plurality of storage means for each detector, each associated with a distinct time interval, and

means for sequentially switching said collecting or detecting means to said storage means.

2. The analog-processing readout chip of claim 1 wherein each of said storage means is a capacitor.

3. The analog-processing readout chip of claim 1 wherein drive and output electronics comprises adapted to read out said signal data in digitized form in real time.

4. The analog-processing readout chip of claim 1 wherein said collecting or detecting means comprises anodes.

5. The analog-processing readout chip of claim 1 wherein said collecting or detecting means comprises PIN diodes.

6. The analog-processing readout chip of claim 1 wherein said collecting or detecting means comprises an array hybrid of PIN diodes which are each electrically connected to said readout electronics on said analog-processing readout chip by metal bumps.

7. The analog-processing readout chip of claim 1 wherein said readout electronics comprises a shift register adapted to sequence between said storage capacitors.

8. The analog-processing readout chip of claim 1 wherein said readout electronics is adapted for direct readout with a source follower for each unit cell.

9. The analog-processing readout chip of claim 1 wherein said analog-processing readout chip comprises a current driver adapted to drive the data signals off the chip.

10. The analog-processing readout chip of claim 1 wherein said analog-processing readout chip is adapted to complete a processing cycle during an integration time interval less than 20 ns.

11. The analog-processing readout chip of claim 1 wherein said analog-processing readout chip is adapted to reset is a time interval less than 10 ns.

12. The analog-processing readout chip of claim 1 wherein said analog-processing readout chip comprises a delta reset circuit for enhanced signal to noise ratio.

13. The analog-processing readout chip of claim 1 wherein said analog-processing readout chip comprises bulk silicon CMOS components.

14. The analog-processing readout chip of claim 1 wherein said analog-processing readout chip comprises silicon on sapphire CMOS components.

15. The analog-processing readout chip of claim 1 wherein said means for sequentially switching comprises a two dimensional array of storage means having rows and columns and in which all the columns are input to a single multiplexer.

16. The analog-processing readout chip of claim 15 wherein said plurality of means for collecting or detecting signal data comprises a high speed shift register to select by time interval the capacitor for storing a signal in a storage capacity.

17. A processing readout chip comprising

a plurality of means for collecting or detecting signal data and

readout electronics comprising

a plurality of storage means for each detector, each associated with a distinct time interval, and means for sequentially switching said collecting or detecting means to said storage means.