Semiconductor memory device
First Claim
1. A semiconductor memory device comprising:
- a plurality of memory cell blocks each including a plurality of memory cells for storing data therein;
data input buffer means for buffering an input data signal;
data register means for storing said input data signal therein;
first switching means for transferring said input data signal to said data register means;
register set control logic means for controlling said first switching means;
register set decoding means for decoding an output signal from said register set control logic means and a first address signal to transfer said input data signal to said data register means;
write data drive means for transferring an output data signal from said data input buffer means or said data register means to a selected one of said memory cells;
first data transfer means for transferring the output data signal from said data input buffer means to said write data drive means;
second data transfer means for transferring the output data signal from said data register means to said write data drive means;
data transfer control means for generating first and second control signals to control said first and second data transfer means, respectively; and
data register output control means for decoding the second control signal from said data transfer control means and a second address signal to transfer the output data signal from said data register means to said write data drive means through said second data transfer means.
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Accused Products
Abstract
A semiconductor memory device comprising a plurality of memory cells for storing data therein, a data input buffer circuit for buffering an input data signal, a data register circuit for storing the input data signal therein, a switching element for transferring the input data signal to the data register circuit, a register set control logic unit for controlling the switching element, a register set decoding circuit for decoding an output signal from the register set control logic unit and a first address signal, a write data drive circuit for transferring an output data signal from the data input buffer circuit or the data register circuit to a selected one of the memory cells, a first data transfer element for transferring the output data signal from the data input buffer circuit to the write data drive circuit, a second data transfer element for transferring the output data signal from the data register circuit to the write data drive circuit, a data transfer control circuit for generating first and second control signals to control the first and second data transfer element, respectively, and a data register output control circuit for decoding the second control signal from the data transfer control circuit and a second address signal.
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Citations
14 Claims
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1. A semiconductor memory device comprising:
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a plurality of memory cell blocks each including a plurality of memory cells for storing data therein; data input buffer means for buffering an input data signal; data register means for storing said input data signal therein; first switching means for transferring said input data signal to said data register means; register set control logic means for controlling said first switching means; register set decoding means for decoding an output signal from said register set control logic means and a first address signal to transfer said input data signal to said data register means; write data drive means for transferring an output data signal from said data input buffer means or said data register means to a selected one of said memory cells; first data transfer means for transferring the output data signal from said data input buffer means to said write data drive means; second data transfer means for transferring the output data signal from said data register means to said write data drive means; data transfer control means for generating first and second control signals to control said first and second data transfer means, respectively; and data register output control means for decoding the second control signal from said data transfer control means and a second address signal to transfer the output data signal from said data register means to said write data drive means through said second data transfer means. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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Specification