Semiconductor memory device

• US 5,696,720 A
• Filed: 12/27/1996
• Issued: 12/09/1997
• Est. Priority Date: 12/29/1995
• Status: Expired due to Term

• Current Assignee: Hyundai Electronics Industries Co. Ltd. (SK Hynix Inc.)
• Original Assignee: Hyundai Electronics Industries Co. Ltd. (SK Hynix Inc.)
• Inventors: Lee, Jae Jin
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): Nguyen, Hien
• Application Number:
  US08/777,199
• Time in Patent Office: 347 Days
• Field of Search: 365/189.05, 365/189.01, 365/230.08, 365/189.08
• US Class Current: 365/189.05
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits

Abstract

A semiconductor memory device comprising a plurality of memory cells for storing data therein, a data input buffer circuit for buffering an input data signal, a data register circuit for storing the input data signal therein, a switching element for transferring the input data signal to the data register circuit, a register set control logic unit for controlling the switching element, a register set decoding circuit for decoding an output signal from the register set control logic unit and a first address signal, a write data drive circuit for transferring an output data signal from the data input buffer circuit or the data register circuit to a selected one of the memory cells, a first data transfer element for transferring the output data signal from the data input buffer circuit to the write data drive circuit, a second data transfer element for transferring the output data signal from the data register circuit to the write data drive circuit, a data transfer control circuit for generating first and second control signals to control the first and second data transfer element, respectively, and a data register output control circuit for decoding the second control signal from the data transfer control circuit and a second address signal.

Claims

1. A semiconductor memory device comprising:

a plurality of memory cell blocks each including a plurality of memory cells for storing data therein;

data input buffer means for buffering an input data signal;

data register means for storing said input data signal therein;

first switching means for transferring said input data signal to said data register means;

register set control logic means for controlling said first switching means;

register set decoding means for decoding an output signal from said register set control logic means and a first address signal to transfer said input data signal to said data register means;

write data drive means for transferring an output data signal from said data input buffer means or said data register means to a selected one of said memory cells;

first data transfer means for transferring the output data signal from said data input buffer means to said write data drive means;

second data transfer means for transferring the output data signal from said data register means to said write data drive means;

data transfer control means for generating first and second control signals to control said first and second data transfer means, respectively; and

data register output control means for decoding the second control signal from said data transfer control means and a second address signal to transfer the output data signal from said data register means to said write data drive means through said second data transfer means.

2. A semiconductor memory device as set forth in claim 1, wherein said data register means includes:

a plurality of latch means each for temporarily storing said input data signal transferred by said first switching means therein;

a plurality of second switching means each for transferring said input data signal transferred by said first switching means to a corresponding one of said latch means; and

a plurality of third switching means each for transferring said input data signal stored in a corresponding one of said latch means to said second data transfer means.

3. A semiconductor memory device as set forth in claim 2, wherein each of said second and third switching means includes a MOS transistor.

4. A semiconductor memory device as set forth in claim 3, wherein said MOS transistor is of an N type.

5. A semiconductor memory device as set forth in claim 2, wherein each of said latch means includes a plurality of inverters.

6. A semiconductor memory device as set forth in claim 1, wherein said first switching means include a MOS transistor.

7. A semiconductor memory device as set forth in claim 6, wherein said MOS transistor is of an N type.

8. A semiconductor memory device as set forth in claim 1, wherein said first data transfer means include a MOS transistor.

9. A semiconductor memory device as set forth in claim 8, wherein said MOS transistor is of an N type.

10. A semiconductor memory device as set forth in claim 1, wherein said second data transfer means include a MOS transistor.

11. A semiconductor memory device as set forth in claim 10, wherein said MOS transistor is of an N type.

12. A semiconductor memory device as set forth in any one of claim 1, wherein said register set control logic means is adapted to turn on said first switching means when a column address strobe bar signal is first enabled and a row address strobe bar signal and a write enable signal are then enabled simultaneously.

13. A semiconductor memory device as set forth in any one of claim 1, wherein said data transfer control means is adapted to turn on said first data transfer means when a desired address signal has a first logic value under the condition that a column address strobe bar signal, a row address strobe bar signal and a write enable signal are all enabled and to turn on said second data transfer means when said desired address signal has a second logic value under the condition that said column address strobe bar signal, row address strobe bar signal and write enable signal are all enabled.

14. A semiconductor memory device as set forth in claim 13, wherein said first logic value is high and said second logic value is low.