Burst EDO memory device

• US 5,696,732 A
• Filed: 11/21/1996
• Issued: 12/09/1997
• Est. Priority Date: 12/23/1994
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Williams, Brett L., Zagar, Paul S.
• Primary Examiner(s): Nguyen, Tan T.
• Application Number:
  US08/754,780
• Time in Patent Office: 383 Days
• Field of Search: 365/233.5, 365/233, 365/238.5, 365/230.01, 365/230.08
• US Class Current: 365/233.5
• CPC Class Codes: G06F 12/0638 Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G11C 11/407 for memory cells of the field-effect type
• CPC Class Codes: G11C 7/1018 Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
• CPC Class Codes: G11C 7/1021 Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
• CPC Class Codes: G11C 7/1024 Extended data output [EDO] mode, i.e. keeping output buffer enabled during an extended period of time
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/109 Control signal input circuits
• CPC Class Codes: G11C 7/1096 Write circuits, e.g. I/O line write drivers

Abstract

An integrated circuit memory device is designed for high speed data access and for compatibility with existing memory systems. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at the device cycle frequency. Transitions of the Read/Write control line during a burst access will terminate the burst access, reset the burst length counter and initialize the device for another burst access. The device is compatible with existing Extended Data Out DRAM device pinouts, Fast Page Mode and Extended Data Out Single In-Line Memory Module pinouts, and other memory circuit designs.

Claims

1. A method of accessing a further memory element of a memory device, the memory device having an array of memory elements, where one of the elements has been identified and accessed, the memory device includes an address latch, an address counter, an address strobe node for receiving a column address strobe, and an output data, the method comprising:

providing the address of the further element from within the memory device and accessing the further element, in response to a transition of an address latch signal the step of providing the address further comprising the sub-steps of;

applying a first column address strobe to the address strobe node for latching a first column address;

accessing a first memory element of the array of memory elements at the first column address;

applying a second column address strobe to the address strobe node for advancing

the column address within the memory device to specify a second column address;

accessing a second memory element of the array of memory elements at the second column address;

switching data driven to an external data node from a logic low level to a logic high level in response to a single transition of the column address strobe; and

maintaining a high impedance state on the output data driver at least until said step of applying the second column address strobe.

2. The method of claim 1, further comprising:

driving data from the one element of the memory device after a plurality of transitions of the address latch signal.

3. The method of claim 1, further comprising the steps of:

applying a third column address strobe to the address strobe node for advancing the column address to specify a third column address; and

latching an output of the memory device from the first column address in synchronization with the third column address strobe.

4. The method of claim 3, further comprising the step of:

selecting a burst mode of operation of the memory device prior to said applying the first column address strobe.