Burst EDO memory device
First Claim
1. A method of accessing a further memory element of a memory device, the memory device having an array of memory elements, where one of the elements has been identified and accessed, the memory device includes an address latch, an address counter, an address strobe node for receiving a column address strobe, and an output data, the method comprising:
- providing the address of the further element from within the memory device and accessing the further element, in response to a transition of an address latch signal the step of providing the address further comprising the sub-steps of;
applying a first column address strobe to the address strobe node for latching a first column address;
accessing a first memory element of the array of memory elements at the first column address;
applying a second column address strobe to the address strobe node for advancingthe column address within the memory device to specify a second column address;
accessing a second memory element of the array of memory elements at the second column address;
switching data driven to an external data node from a logic low level to a logic high level in response to a single transition of the column address strobe; and
maintaining a high impedance state on the output data driver at least until said step of applying the second column address strobe.
1 Assignment
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Accused Products
Abstract
An integrated circuit memory device is designed for high speed data access and for compatibility with existing memory systems. An address strobe signal is used to latch a first address. During a burst access cycle the address is incremented internal to the device with additional address strobe transitions. A new memory address is only required at the beginning of each burst access. Read/Write commands are issued once per burst access eliminating the need to toggle the Read/Write control line at the device cycle frequency. Transitions of the Read/Write control line during a burst access will terminate the burst access, reset the burst length counter and initialize the device for another burst access. The device is compatible with existing Extended Data Out DRAM device pinouts, Fast Page Mode and Extended Data Out Single In-Line Memory Module pinouts, and other memory circuit designs.
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Citations
4 Claims
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1. A method of accessing a further memory element of a memory device, the memory device having an array of memory elements, where one of the elements has been identified and accessed, the memory device includes an address latch, an address counter, an address strobe node for receiving a column address strobe, and an output data, the method comprising:
providing the address of the further element from within the memory device and accessing the further element, in response to a transition of an address latch signal the step of providing the address further comprising the sub-steps of; applying a first column address strobe to the address strobe node for latching a first column address; accessing a first memory element of the array of memory elements at the first column address; applying a second column address strobe to the address strobe node for advancing the column address within the memory device to specify a second column address; accessing a second memory element of the array of memory elements at the second column address; switching data driven to an external data node from a logic low level to a logic high level in response to a single transition of the column address strobe; and maintaining a high impedance state on the output data driver at least until said step of applying the second column address strobe. - View Dependent Claims (2, 3, 4)
Specification