Device for the serial transmission of data between at least two terminals

• US 5,696,777 A
• Filed: 01/26/1995
• Issued: 12/09/1997
• Est. Priority Date: 02/08/1994
• Status: Expired due to Term

• Current Assignee: Robert Bosch GmbH
• Original Assignee: Robert Bosch GmbH
• Inventors: Hofsaess, Michael
• Primary Examiner(s): CHUNG, PHUNG M
• Application Number:
  US08/378,422
• Time in Patent Office: 1,048 Days
• Field of Search: 371/67.1, 371/20.1, 371/63, 371/20, 371/20.4, 371/20.6, 371/68.2, 371/68.1, 371/22.1, 371/36, 371/57.2, 324/509, 324/541, 327/74, 327/75, 327/76, 370/24, 370/13, 370/14, 370/15, 370/16, 370/17, 370/242, 370/248, 370/249, 395/182.02, 395/185.09, 395/185.01, 395/185.04
• US Class Current: 714/820
• CPC Class Codes: G01R 31/52 Testing for short-circuits, leakage current or ground faults
• CPC Class Codes: H04L 1/00 Arrangements for detecting or preventing errors in the information received correcting synchronisation H04L7/00
• CPC Class Codes: H04L 25/0272 Arrangements for coupling to multiple lines, e.g. for differential transmission
• CPC Class Codes: H04L 25/0278 Arrangements for impedance matching
• CPC Class Codes: H04L 25/028 Arrangements specific to the transmitter end
• CPC Class Codes: H04L 25/0292 Arrangements specific to the receiver end

Abstract

A device for the serial transmission of data between at least two terminals which are interconnected via a two-wire line. Each terminal has a bus-coupling circuit having at least one transmitting section or one receiving section. The transmitting section has at least two driver circuits which are each connected to one line of the two-wire line. A resistor network is switched between each driver circuit and line. During a data transmission, the transmitting section transmits complementary signals to the lines. The receiving section has a comparator which is connected at its one input to a line of the two-wire line and which is supplied at its second input with a specific reference potential. The output signals from the comparators are evaluated by an evaluation circuit. The reference potentials of the comparators and the resistor networks are designed to allow both comparators to emit a switching signal, in dependence upon the transmitted bit conditions, in the case of an error-free operation. The reference potentials and the resistor networks are designed to allow one of the comparators to emit a switching signal, in dependence upon the transmitted bit conditions, and to allow the other comparator to remain in one of the two circuit states, in the case of a short-circuit of one of the lines to any voltage potential whatsoever or in the case of a short-circuit of the lines between themselves.

Claims

1. A device for a serial transmission of data between at least two terminals, one of the at least two terminals for transmitting data and one of the at least two terminals for receiving the transmitted data, the at least two terminals being connected via a two-wire line, comprising:

a bus-coupling circuit in each of the at least two terminals, the bus-coupling circuit in the terminal for transmitting data having at least one transmitting section and the bus-coupling circuit in the terminal for receiving the transmitted data having at least one receiving section, the bus-coupling circuit being controlled by a control unit;

wherein the at least one transmitting section receives the serial transmission of data and includes a first driver circuit and a second driver circuit, the first driver circuit being connected to a first wire of the two-wire line and providing a first signal on the first wire determined as a function of the transmitted data, the second driver circuit being connected to a second wire of the two-wire line and providing a second signal on the second wire determined as a function of the transmitted data, the second signal being complementary of the first signal;

wherein the at least one receiving section includes at least a first comparator and a second comparator, the first comparator having a first input connected to the first wire, a second input connected to a first preselected reference potential, and a first output signal, the second comparator having a third input connected to the second wire, a fourth input connected to a second preselected reference potential, and a second output signal;

a resistor network coupled between the first driver circuit, the second driver circuit, the first wire and the second wire, wherein the first driver circuit is connected via a first resistor to the first wire, the second driver circuit is connected via a second resistor to the second wire, the first wire being connected via a third resistor to a first supply potential, the second wire being connected via a fourth resistor to a second supply potential, and wherein a first resistance ratio of the first resistor to the second resistor is substantially the same as a second resistance ratio of the third resistor to the fourth resistor, each of the first and second resistance ratios having a value other than one;

an evaluation circuit coupled to the first comparator and to the second comparator, the evaluation circuit receiving the first output signal and the second output signal to determine whether the two-wire line is in one of a first state representing an error-free condition and a second state representing an error condition;

wherein when the two-wire line is in the first state, the evaluation circuit performs a first operation on the first output signal and the second output signal to obtain a first result dependent upon the first output signal and the second output signal, and when the two-wire line is in the second state, the evaluation circuit performs a second operation on the first output signal and the second output signal to obtain a second result dependent upon one of the first output signal and the second output signal.

2. The device according to claim 1, wherein the second supply potential includes a ground potential.

3. A device for a serial transmission of data between at least two terminals, one of the at least two terminals for transmitting data and one of the at least two terminals for receiving the transmitted data, the at least two terminals being connected via a two-wire line, comprising:

a bus-coupling circuit in each of the at least two terminals, the bus-coupling circuit in the terminal for transmitting data having at least one transmitting section and the bus-coupling circuit in the terminal for receiving the transmitted data having at least one receiving section, the bus-coupling circuit being controlled by a control unit;

wherein the at least one transmitting section receives the serial transmission of data and includes a first driver circuit and a second driver circuit, the first driver circuit being connected to a first wire of the two-wire line and providing a first signal on the first wire determined as a function of the transmitted dam, the second driver circuit being connected to a second wire of the two-wire line and providing a second signal on the second wire determined as a function of the transmitted dam, the second signal being complementary of the first signal;

wherein the at least one receiving section includes at least a first comparator and a second comparator, the first comparator having a first input connected to the first wire, a second input connected to a first preselected reference potential, and a first output signal, the second comparator having a third input connected to the second wire, a fourth input connected to a second preselected reference potential, and a second output signal;

a resistor network coupled between the first driver circuit, the second driver circuit, the first wire and the second wire;

an evaluation circuit coupled to the first comparator and to the second comparator, the evaluation circuit receiving the first output signal and the second output signal to determine whether the two-wire line is in one of a first state representing an error-free condition and a second state representing an error condition;

wherein when the two-wire line is in the first state, the evaluation circuit performs a first operation on the first output signal and the second output signal to obtain a first result dependent upon the first output signal and the second output signal, and when the two-wire line is in the second state, the evaluation circuit performs a second operation on the first output signal and the second output signal to obtain a second result dependent upon one of the first output signal and the second output signal, and wherein when the two-wire line is in the second state of the short circuit between the first wire and the second wire, the first preselected reference potential includes a value between a range of potentials resulting from the short circuit between the first wire and the second wire, and the second preselected reference potential is outside the range of potentials.

4. The device according to claim 3, wherein the first preselected reference potential is approximately midway between the range of potentials.

5. A device for a serial transmission of data between at least two terminals, one of the at least two terminals for transmitting data and one of the at least two terminals for receiving the transmitted data, the at least two terminals being connected via a two-wire line, comprising:

a bus-coupling circuit in each of the at least two terminals, the bus-coupling circuit in the terminal for transmitting data having at least one transmitting section and the bus-coupling circuit in the terminal for receiving the transmitted data having at least one receiving section, the bus-coupling circuit being controlled by a control unit;

wherein the at least one transmitting section receives the serial transmission of data and includes a first driver circuit and a second driver circuit, the first driver circuit being connected to a first wire of the two-wire line and providing a first signal on the first wire determined as a function of the transmitted dam, the second driver circuit being connected to a second wire of the two-wire line and providing a second signal on the second wire determined as a function of the transmitted data, the second signal being complementary of the first signal;

wherein the at least one receiving section includes at least a first comparator and a second comparator, the first comparator having a first input connected to the first wire, a second input connected to a first preselected reference potential, and a first output signal, the second comparator having a third input connected to the second wire, a fourth input connected to a second preselected reference potential, and a second output signal;

a resistor network coupled between the first driver circuit, the second driver circuit, the first wire and the second wire;

an evaluation circuit coupled to the first comparator and to the second comparator, the evaluation circuit receiving the first output signal and the second output signal to determine whether the two-wire line is in one of a first state representing an error-free condition and a second state representing an error condition;

wherein when the two-wire line is in the first state, the evaluation circuit performs a first operation on the first output signal and the second output signal to obtain a first result dependent upon the first output signal and the second output signal, and when the two-wire line is in the second state, the evaluation circuit performs a second operation on the first output signal and the second output signal to obtain a second result dependent upon one of the first output signal and the second output signal, and wherein the first operation performed by the evaluation circuit includes an AND logic operation and the second operation performed by the evaluation circuit includes an OR logic operation.

6. The device according to claim 5, wherein a selection of one of the AND logic operation and the OR logic operation to be performed by the evaluation circuit is determined by a logic circuit of the evaluation circuit as a function of the first output signal and the second output signal, the selection of one of the AND logic operation and the OR logic operation being stored in a bistable circuit element, each state of the bistable circuit element corresponding to one of the AND logic operation and the OR logic operation.

7. The device according to claim 6, wherein

the logic circuit includes a first AND gate having the first output signal and the second output signal as inputs,

a first OR gate having an inverted output coupled to an inverter circuit, the first OR gate having the first output signal and the second output signal as inputs,

the bistable circuit element having a set input coupled to an output of the first AND gate, a reset input coupled to the inverted output of the first OR gate, an output coupled to an input of a second AND gate, and an inverted output coupled to an input of a third AND gate,

the second AND gate having a second input coupled to the output of the first AND gate and an output coupled to an input of a second OR gate, and

the third AND gate having a second input coupled to an output of the inverter circuit and an output coupled to the second OR gate.

8. A method for serially transmitting data between at least two terminals, one of the at least two terminals for transmitting data and one of the at least two terminals for receiving the transmitted data, the at least two terminals being connected via a two-wire line, comprising the steps of:

receiving serially transmitted data in a first bus-coupling circuit of the terminal for transmitting data, the first bus-coupling circuit having at least one transmitting section and being controlled by a first microcomputer;

providing a first signal on a first wire of the two-wire line determined as a function of the transmitted data;

providing a second signal on a second wire of the two-wire line determined as a function of the transmitted data, the second signal being complementary of the first signal;

receiving the transmitted data, via the first signal on the first wire and the second signal on the second wire, in a second bus-coupling circuit in the terminal for receiving the transmitted data, the second bus-coupling circuit having at least one receiving section;

comparing the first signal to a first selected reference potential to generate a first output signal and comparing the second signal to a second selected reference potential to generate a second output signal;

evaluating the first output signal and the second output signal to determine one of an error-free state of the two-wire line and an error-condition state of the two-wire line;

when the two-wire line is in an error-free state, performing a first operation on the first output signal and the second output signal to obtain a result based on the first output signal and the second output signal; and

when the two-wire line is in an error-condition state, performing a second operation on the first output signal and the second output signal to obtain a result based on one of the first output signal and the second output signal, wherein the error-condition state of the two-wire line includes one of a short circuit of the first wire to a voltage, a short circuit of the second wire to the voltage, and a short circuit between the first wire and the second wire, and wherein when the two-wire line is in the error-condition state of the short circuit between the first wire and the second wire, the first selected reference potential includes a value between a range of potentials resulting from the short circuit between the first wire and the second wire, and the second selected reference potential is outside the range of potentials.

9. A method for serially transmitting data between at least two terminals, one of the at least two terminals for transmitting data and one of the at least two terminals for receiving the transmitted data, the at least two terminals being connected via a two-wire line, comprising the steps of:

receiving serially transmitted data in a first bus-coupling circuit of the terminal for transmitting data, the first bus-coupling circuit having at least one transmitting section and being controlled by a first microcomputer;

providing a first signal on a first wire of the two-wire line determined as a function of the transmitted data;

providing a second signal on a second wire of the two-wire line determined as a function of the transmitted data, the second signal being complementary of the first signal;

receiving the transmitted data, via the first signal on the first wire and the second signal on the second wire, in a second bus-coupling circuit in the terminal for receiving the transmitted data, the second bus-coupling circuit having at least one receiving section;

comparing the first signal to a first selected reference potential to generate a first output signal and comparing the second signal to a second selected reference potential to generate a second output signal;

evaluating the first output signal and the second output signal to determine one of an error-free state of the two-wire line and an error-condition state of the two-wire line;

when the two-wire line is in an error-free state, performing a first operation on the first output signal and the second output signal to obtain a result based on the first output signal and the second output signal; and

when the two-wire line is in an error-condition state, performing a second operation on the first output signal and the second output signal to obtain a result based on one of the first output signal and the second output signal,

wherein the step of performing the first operation includes an AND logic operation and the step of performing the second operation includes an OR logic operation, and further comprising the step of selecting one of the AND logic operation and the OR logic operation as a function of the first output signal and the second output signal, the selection of one of the AND logic operation and the OR logic operation being stored in a bistable circuit element, each state of the bistable circuit element corresponding to one of the AND logic operation and the OR logic operation.