Method and apparatus for performing burst read operations in an asynchronous nonvolatile memory

• US 5,696,917 A
• Filed: 06/03/1994
• Issued: 12/09/1997
• Est. Priority Date: 06/03/1994
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: McCormick, Bruce, Mills, Duane R., Pashley, Richard D., Sambandan, Sachidanandan, Dipert, Brian Lyn
• Primary Examiner(s): Kim, Matthew M.
• Application Number:
  US08/253,499
• Time in Patent Office: 1,285 Days
• Field of Search: 395/250, 395/200.13, 395/894, 395/307, 395/308, 395/240.3, 395/428-433, 395/401, 395/410, 395/855
• US Class Current: 711/1
• CPC Class Codes: G06F 12/0607 Interleaved addressing
• CPC Class Codes: G06F 12/08 in hierarchically structured memory systems, e.g. virtual memory systems
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

An asynchronous nonvolatile memory includes a plurality of individual memory components. A burst read operation references consecutive addresses beginning with a first address, wherein the consecutive addresses are not located in a same memory component. A method of performing a burst read operation in the asynchronous nonvolatile memory includes the step of providing the first address as a current address to the plurality of individual components. A current page identified by m higher order bits of the current address is selected. Each of the individual memory components senses a location identified by the m higher order bits. An output of a selected individual memory component is enabled in accordance with n lower bits of the current address. A consecutive subsequent address is provided, wherein the current address becomes a preceding address and the consecutive subsequent address becomes the current address. The output of another selected individual memory component identified by the n lower order bits of the current address is enabled without generating wait states, if the current and preceding addresses identify a same page. The process of providing consecutive subsequent addresses and enabling the output of a memory component identified by the n lower order bits is repeated as long as the current and preceding addresses identify the same page.

Claims

1. A method of performing a burst read operation in an asynchronous non-volatile memory having a plurality of individual memory components, comprising the steps of:

a) providing a first address as a current address to the plurality of individual memory components, wherein consecutive addresses are not located in a same memory component;

b) selecting a current page of the asynchronous nonvolatile memory identified by m higher order bits of the current address, wherein each of the individual memory components senses a location identified by the m higher order bits of the current address substantially simultaneously;

c) enabling the output of a selected individual memory component in accordance with n lower bits of the current address to provide data associated with the current address;

d) providing a consecutive subsequent address, wherein the current address becomes a preceding address, wherein the consecutive subsequent address becomes the current address;

e) enabling the output of another selected individual memory component identified by n lower order bits of the current address without generating wait states to provide data associated with the current address, if the current and preceding addresses identify a same page;

f) repeating steps d) thru e) as long as the current and preceding addresses identify the same page.

2. The method of claim 1 further comprising the steps of:

g) performing the following steps if the current and preceding addresses do not identify the same page;

i) generating wait states;

ii) selecting another page as the current page of the asynchronous nonvolatile memory, wherein the another page is identified by m higher order bits of the current address;

h) returning to step c).

3. The method of claim 1 wherein step a) includes the step of:

i) providing a chip enable signal to the plurality of individual memory components.

4. The method of claim 1 wherein step c) includes the step of:

i) providing an output enable signal to the selected individual memory component.

5. The method of claim 1 wherein the nonvolatile memory is a flash memory.

6. The method of claim 1 wherein a processor performs step d).

7. A computer system comprising:

a processor for initiating a burst read for a range of memory defined by a start address and a plurality of subsequent consecutive addresses;

an asynchronous main memory bus coupled to the processor;

a nonvolatile memory comprising a plurality of individual memory components, wherein consecutive addresses within the nonvolatile memory are not located in a same individual memory component;

a fully programmable gate array (FPGA) coupled to the asynchronous main memory bus and the nonvolatile memory, wherein for each selected address of the memory range, the FPGA selects a page of the nonvolatile memory in accordance with m higher order bits of the selected address, wherein the FPGA enables the output of one of the individual memory components in accordance with n lower order bits of the selected address to provide data to the processor, wherein no wait states are generated as long as the selected address and a preceding address identify a same page of the nonvolatile memory.

8. The computer system of claim 7 wherein the nonvolatile memory is a flash nonvolatile memory.

9. The computer system of claim 7 wherein the asynchronous main memory bus operates at frequencies greater than or equal to 16 MHz.

10. The computer system of claim 7 wherein the processor provides the plurality of subsequent consecutive addresses.

11. The computer system of claim 7 wherein the processor is a static microprocessor.