Memory paging system and method including compressed page mapping hierarchy
First Claim
1. A memory paging system for a computer having a memory and an execution unit addressing the memory using virtual addresses, the memory paging system comprising:
- an address mapping hierarchy, the address mapping hierarchy including a plurality of page tables having page table entries mapping from a first portion of virtual addresses to respective pages in physical memory;
a compressed page mapping hierarchy, the compressed page mapping hierarchy including a plurality of compressed page tables having compressed page table entries mapping from the first portion of virtual addresses to respective compressed pages in physical memory;
a translation lookaside buffer for caching recently used ones of the mappings from the first portion of virtual addresses to respective pages in physical memory; and
a compression/decompression component including a compression/decompression engine coupled between the memory and the execution unit for alternately compressing and decompression pages in memory in respective correspondence with spills from and loads to the translation lookaside buffer.
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Accused Products
Abstract
A memory paging and compression system for a computer having a memory and an execution unit includes an address mapping hierarchy, a compressed page mapping hierarchy, a translation lookaside buffer, and a compression/decompression component. The address mapping hierarchy includes page tables having page table entries which map from a first portion of virtual addresses to respective pages in physical memory. The compressed page mapping hierarchy includes compressed page tables having compressed page table entries mapping from the first portion of virtual addresses to respective compressed pages in physical memory. The translation lookaside buffer caches recently used ones of the mappings from the first portion of virtual addresses to respective pages in physical memory. The compression/decompression component includes a compression/decompression engine coupled between a memory and an execution unit for alternately compressing and decompression pages in memory in respective correspondence with spills from and loads to the translation lookaside buffer. The address mapping hierarchy and compressed page mapping hierarchy may be represented in memory and the compression/decompression component may further include a decompression fault handler and a compression fault handler, each executable on the execution unit.
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Citations
21 Claims
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1. A memory paging system for a computer having a memory and an execution unit addressing the memory using virtual addresses, the memory paging system comprising:
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an address mapping hierarchy, the address mapping hierarchy including a plurality of page tables having page table entries mapping from a first portion of virtual addresses to respective pages in physical memory; a compressed page mapping hierarchy, the compressed page mapping hierarchy including a plurality of compressed page tables having compressed page table entries mapping from the first portion of virtual addresses to respective compressed pages in physical memory; a translation lookaside buffer for caching recently used ones of the mappings from the first portion of virtual addresses to respective pages in physical memory; and a compression/decompression component including a compression/decompression engine coupled between the memory and the execution unit for alternately compressing and decompression pages in memory in respective correspondence with spills from and loads to the translation lookaside buffer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. In a memory paging system for a computer having an execution unit, a memory including a hierarchy of data stores for encoding a mapping from virtual memory addresses to physical memory addresses, and a translation lookaside buffer for caching recently-used virtual to physical address mappings, a compression/decompression subsystem comprising:
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a compression/decompression engine coupled between the execution unit and the memory for alternately compressing and expanding memory-resident pages; means residing in the hierarchy of data stores for identifying a compression state of memory-resident pages, the compression state identifying means triggering a compression fault upon a spill from the translation lookaside buffer, the compression state identifying means triggering a decompression fault upon an access to a memory page not represented in the translation lookaside buffer and identified as compressed by the compression state identifying means; a decompression fault handler responsive to the decompression fault, the decompression fault handler allocating memory for a decompressed memory page, triggering a decompression operation of the compression/decompression engine, and updating the hierarchy of data stores in accordance with the decompression operation; and a compression fault handler responsive to the compression fault, the compression fault handler scanning a free-list for a target memory block, triggering compression operation of the compression/decompression engine, and updating the hierarchy of data stores in accordance with the compression operation. - View Dependent Claims (13, 14, 15)
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16. In a memory paging and compression system, a method for handling a decompression fault arising from a faulting memory access, the method comprising the steps of:
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allocating a new memory page; supplying a physical address of the new memory page to a compression/decompression engine; supplying a virtual address of the faulting memory access to the compression/decompression engine; triggering decompression by the compression/decompression engine, the decompression being from a compressed representation of the page corresponding to the faulting memory access to an uncompressed representation of same at the new memory page; and updating an address mapping hierarchy to indicate the physical address of the new memory page and uncompressed state of the corresponding page. - View Dependent Claims (17, 18)
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19. In a memory paging and compression system, a method for handling a compression fault, the method comprising the steps of:
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scanning a free-list for a new block in a compressed memory space; supplying a physical address of the new block to a compression/decompression engine; supplying a virtual address of a faulting memory access to the compression/decompression engine; triggering compression by the compression/decompression engine, the compression being from an uncompressed representation of the page corresponding to the faulting memory access to an compressed representation of same at the new block; updating an address mapping hierarchy to indicate a compressed state of the corresponding page; and updating a compressed page mapping hierarchy to indicate the physical address and size of the corresponding compressed representation. - View Dependent Claims (20, 21)
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Specification