Device for converting data using look-up tables

• US 5,696,941 A
• Filed: 02/01/1995
• Issued: 12/09/1997
• Est. Priority Date: 02/02/1994
• Status: Expired

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Jung, Lee-wha
• Primary Examiner(s): LOUIS JACQUES, JACQUES H
• Application Number:
  US08/382,208
• Time in Patent Office: 1,042 Days
• Field of Search: 395/500, 395/164, 395/501, 395/508, 395/515, 360/45, 360/32, 382/299, 382/300, 358/447, 358/404, 358/451, 358/455-457, 358/523, 358/433, 358/442-445, 358/468, 358/479, 348/654, 348/514, 348/651, 348/671, 348/674, 348/620, 348/717, 348/472, 348/44, 345/199, 345/191, 345/22, 345/197
• US Class Current: 710/3
• CPC Class Codes: G06T 5/92 based on global image properties
• CPC Class Codes: H04N 1/6019 using look-up tables H04N1/6025 takes precedence

Abstract

A data converting device for converting data by employing a plurality of LUTs stored in a single memory device. The device generates, with reference to two or more LUTs sequentially, a converted output data corresponding to input data and converting level selected by each LUT. The data converting device has a single memory device for storing two or more LUTs corresponding to the number of data converting modes by block units, each block including a plurality of sub-LUTs corresponding to the number of converting levels defined in each corresponding converting mode. The device also has an address generator for generating an address for accessing the memory device by an input data, by the data selected among the output data read from the memory device and by the data for selecting a converting level in each converting mode, the address being generated repeatedly a number of times which corresponds to the number of LUTs stored in the memory device, to thereby minimize the bulk of the memory device, and thus enable the miniaturization of the data converting device.

Claims

1. A data converting device for generating output data converted corresponding to input data and a conversion level selected by look-up-tables (LUTs) with sequential reference to three or more LUTs, said data converting device comprising:

a single memory device for storing at least three LUTs corresponding to a number of data converting modes by block units, each of said block units including a plurality of sub-LUTs corresponding to a number of conversion levels defined in each corresponding conversion mode; and

an address generator for generating a series of addresses for accessing said memory device, a first address of said series of addresses being determined according to first conversion level data and input data, each address of said series of addresses following said first address being determined using corresponding conversion level data and data read out from one of said LUTs using a next previous address of said series of addresses, the number of addresses in said series being equal to the number of LUTs stored in said memory device, wherein a final address of said series of addresses indicates a location in said memory device where final output data is stored.

2. A data converting device according to claim 1, wherein said address generator comprises:

a first address generator for generating a first portion of each of said series of addresses to sequentially select an LUT stored in said memory device;

a second address generator for generating a second portion of each of said series of addresses to select a sub-LUT corresponding to the conversion level selected in the converting mode for said selected LUT;

a third address generator for receiving the output data read from said memory device, and for generating a third portion of each of said series of addresses for selecting converting data corresponding to said input data when said input data is converted according to a first converting mode and for selecting converting data corresponding to the output data read from said memory device when said input data is converted according to a converting mode which is other than said first converting mode; and

a sync signal generator for synchronizing said generated first, second and third addresses so as to access data in said memory device.