Two dimensional frame buffer memory interface system and method of operation thereof

• US 5,696,947 A
• Filed: 11/20/1995
• Issued: 12/09/1997
• Est. Priority Date: 11/20/1995
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Johns, Charles R., Roberson, John T.
• Primary Examiner(s): Tung, Kee M.
• Application Number:
  US08/560,610
• Time in Patent Office: 750 Days
• Field of Search: 395/509, 395/511, 395/517, 395/520, 395/521, 345/185, 345/189, 345/190, 345/200, 345/201, 345/203
• US Class Current: 345/537
• CPC Class Codes: G06F 12/0207 with multidimensional access, e.g. row/column, matrix
• CPC Class Codes: G06F 12/0875 with dedicated cache, e.g. instruction or stack
• CPC Class Codes: G09G 2360/121 using a cache memory
• CPC Class Codes: G09G 5/393 Arrangements for updating the contents of the bit-mapped memory

Abstract

A two dimensional frame buffer memory interface structure is provided. The interface comprises a parallel data bus, a control signal bus, a data cache, and a controller. The parallel data bus transfers a set of pixel data in parallel to the data cache. The control signal bus transfers to the controller a X strobe signal, a Y strobe signal, and a mode signal indicating an interface mode specifying a designated pattern for the pixel data transferred over the parallel data bus. The data cache, controlled by the controller and connected to the parallel data bus, compiles each set of pixel data received over the parallel data bus into the designated pattern of pixels, as indicated by the mode signal. The controller transfers each set of pixel data from the data cache to a two dimensional frame buffer to be stored in the designated pattern at a calculated address, wherein an address in the two dimensional frame buffer is specified by an X address and a Y address and wherein the calculated address for a given set of pixel data is an X address equal to the X address of a previous set of pixel data plus, when a X strobe signal is received for the given set of pixel data, an X increment associated with the indicated interface mode, and a Y address equal to a Y address of the previous set of pixel data plus, when a Y strobe signal is received for the given set of pixel data, a Y increment associated with the indicated interface mode.

Claims

1. A two dimensional frame buffer memory interface structure comprising:

a parallel data bus that transfers a set of pixel data in parallel, said set of pixel data specifying data for a plurality of pixels in a display image;

a control signal bus that transfers an X strobe signal, a Y strobe signal, and a mode signal indicating an interface mode specifying a designated pattern for the pixel data transferred over the parallel data bus;

a controller connected to the control signal bus that receives the X strobe signal, the Y strobe signal, and the mode signal; and

a data cache, controlled by the controller and connected to the parallel data bus, that compiles each set of pixel data received over the parallel data bus into the designated pattern indicated by the mode signal;

wherein the controller transfers each set of pixel data from the data cache to a two dimensional frame buffer for storage in the designated pattern at a respective location, each location in the two dimensional frame buffer having an address including an X address and a Y address, wherein the address of the location of a given set of pixel data includes an X address equal to the X address of a location of a previous set of pixel data plus, when an X strobe signal is received for the given set of pixel data, an X increment associated with the indicated interface mode, and a Y address equal to a Y address of the location of the previous set of pixel data plus, when a Y strobe signal is received for the given set of pixel data, a Y increment associated with the indicated interface mode.

2. A two dimensional frame buffer memory interface structure according to claim 1, wherein the indicated interface mode is a horizontal span mode having an X increment equal to a data width of the parallel data bus and a Y increment equal to one, and wherein the designated pattern is a linear horizontal line of pixels.

3. A two dimensional frame buffer memory interface structure according to claim 1, wherein the indicated interface mode is a vertical span mode having an X increment equal to one and a Y increment equal to a data width of the parallel data bus, and wherein the designated pattern is a linear vertical line of pixels.

4. A two dimensional frame buffer memory interface structure according to claim 1, wherein the indicated interface mode is an array mode having an X increment equal to N and a Y increment equal to M, and wherein the designated pattern is an array of pixels that is N units in an X direction and M units in a Y direction, and further wherein the data width is equal to N×

M.

5. A two dimensional frame buffer memory interface structure according to claim 4, wherein a unit is a pixel.

6. A two dimensional frame buffer memory interface structure according to claim 4, wherein a unit is a bit.

7. A two dimensional frame buffer memory interface structure according to claim 1, further comprising an address bus that transfers an initial address for the pixel data transferred by the parallel data bus, wherein the initial address includes an initial X address and an initial Y address, and wherein a first set of pixel data transferred over the parallel data bus is stored in the two dimensional frame buffer at the location specified by the initial X address and the initial Y address.

8. A two dimensional frame buffer memory interface structure according to claim 1, said plurality of pixels including n pixels, wherein the parallel data bus transfers n enable bits that each correspond to a respective one of said n pixels, and wherein the data cache compiles the n pixels into the designated pattern by setting a given pixel to a first color for a first state of the corresponding enable bit and setting the given pixel to a second color for a second state of the corresponding enable bit.

9. A method of transferring two dimensional data to a frame buffer memory, the method comprising the steps of:

receiving a mode signal indicating an interface mode specifying a designated pattern for pixel data transferred over a parallel data bus;

receiving, over the parallel data bus, a set of pixel data specifying data for n pixels of a display image, n being greater than 1;

compiling the set of pixel data received over the parallel data bus into the designated pattern, as indicated by the mode signal; and

transferring the compiled set of pixel data to a two dimensional frame buffer for storage, in the designated pattern, at a location specified by an address including an X address and a Y address;

wherein the address of the location includes an X address equal to the X address of a previous set of pixel data plus, if an X strobe signal is received, an X increment associated with the indicated interface mode, and a Y address equal to a Y address of the previous set of pixel data plus, if a Y strobe signal is received, a Y increment associated with the indicated interface mode.

10. A method of transferring two dimensional data to a frame buffer memory according to claim 9, wherein the indicated interface mode is a horizontal span mode having an X increment equal to a data width of the parallel data bus and a Y increment equal to one, and wherein the designated pattern is a linear horizontal line of pixels.

11. A method of transferring two dimensional data to a frame buffer memory according to claim 9, wherein the indicated interface mode is a vertical span mode having an X increment equal to one and a Y increment equal to a data width of the parallel data bus, and wherein the designated pattern is a linear vertical line of pixels.

12. A method of transferring two dimensional data to a frame buffer memory according to claim 9, wherein the indicated interface mode is an array mode having an X increment equal to N and a Y increment equal to M, and wherein the designated pattern is an array of pixels that is N units in an X direction and M units in a Y direction, and further wherein the data width is equal to N×

M.

13. A method of transferring two dimensional data to a frame buffer memory according to claim 12, wherein a unit is a pixel.

14. A method of transferring two dimensional data to a frame buffer memory according to claim 12, wherein a unit is a bit.

15. A method of transferring two dimensional data to a frame buffer memory according to claim 9, further comprising an address bus that transfers an initial address for the pixel data transferred by the parallel data bus, wherein the initial address includes an initial X address and an initial Y address, and wherein a first set of pixel data transferred over the parallel data bus is stored in the two dimensional frame buffer at the location specified by the initial X address and the initial Y address.

16. A method of transferring two dimensional data to a frame buffer memory according to claim 9, wherein the parallel data bus transfers n enable bits that each correspond to a respective one of the n pixels, and wherein the data cache compiles the n pixels into the designated pattern by setting a given pixel to a first color for a first state of the corresponding enable bit and setting the given pixel to a second color for a second state of the corresponding enable bit.

17. A frame buffer memory system that receives and stores two dimensional data, comprising:

a parallel data bus that transfers a set of pixel data in parallel, said set of pixel data specifying data for a plurality of pixels in a display image;

a control signal bus that transfers an X strobe signal, a Y strobe signal, and a mode signal indicating an interface mode specifying a designated pattern for the pixel data transferred over the parallel data bus;

a controller connected to the control signal bus that receives the X strobe signal, the Y strobe signal, and the mode signal;

a data cache, controlled by the controller and connected to the parallel data bus, that compiles each set of pixel data received over the parallel data bus into the designated pattern indicated by the mode signal; and

a two dimensional frame buffer, wherein each location in said two dimensional frame buffer has an address including an X address and a Y address;

wherein the controller transfers each set of pixel data from the data cache to the two dimensional frame buffer for storage in the designated pattern at a respective location, the address of the location of a given set of pixel data includes an X address equal to the X address of a previous set of pixel data plus, when a X strobe signal is received for the given set of pixel data, an X increment associated with the indicated interface mode, and a Y address equal to a Y address of the location of the previous set of pixel data plus, when a Y strobe signal is received for the given set of pixel data, a Y increment associated with the indicated interface mode.

18. A frame buffer memory system that receives and stores two dimensional data according to claim 17, wherein the indicated interface mode is a horizontal span mode having an X increment equal to a data width of the parallel data bus and a Y increment equal to one, and wherein the designated pattern is a linear horizontal line of pixels.

19. A frame buffer memory system that receives and stores two dimensional data according to claim 17, wherein the indicated interface mode is a vertical span mode having an X increment equal to one and a Y increment equal to a data width of the parallel data bus, and wherein the designated pattern is a linear vertical line of pixels.

20. A frame buffer memory system that receives and stores two dimensional data according to claim 17, wherein the indicated interface mode is an array mode having an X increment equal to N and a Y increment equal to M, and wherein the designated pattern is an array of pixels that is N units in an X direction and M units in a Y direction, and further wherein the data width is equal to N×

M.

21. A frame buffer memory system that receives and stores two dimensional data according to claim 20, wherein a unit is a pixel.

22. A frame buffer memory system that receives and stores two dimensional data according to claim 20, wherein a unit is a bit.

23. A frame buffer memory system that receives and stores two dimensional data according to claim 17, further comprising an address bus that transfers an initial address for the pixel data transferred by the parallel data bus, wherein the initial address includes an initial X address and an initial Y address, and wherein a first set of pixel data transferred over the parallel data bus is stored in the two dimensional frame buffer at the location specified by the initial X address and the initial Y address.

24. A frame buffer memory system that receives and stores two dimensional data according to claim 17, said plurality of pixels including n pixels, wherein the parallel data bus transfers n enable bits that each correspond to a respective one of said n pixels, and wherein the data cache compiles the n pixels into the designated pattern by setting a given pixel to a first color for a first state of the corresponding enable bit and setting the given pixel to a second color for a second state of the corresponding enable bit.