Nonvolatile semiconductor memory device

• US 5,698,879 A
• Filed: 08/18/1995
• Issued: 12/16/1997
• Est. Priority Date: 08/19/1994
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Aritome, Seiichi, Takeuchi, Ken, Tanaka, Tomoharu
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US08/516,924
• Time in Patent Office: 851 Days
• Field of Search: 257/315, 257/316, 257/319, 257/320, 257/321, 257/322, 257/324, 257/326, 257/390, 257/401, 257/406
• US Class Current: 257/315
• CPC Class Codes: H10B 41/30 characterised by the memory core region
• CPC Class Codes: H10B 41/35 with a cell select transistor, e.g. NAND
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A nonvolatile semiconductor memory device has reduced parasitic capacitance at a select transistor obtained by providing a depletion-mode select transistor with a charge accumulation layer, virtually making a gate insulating film thicker, or providing under the gate insulating film a channel layer that is of a same conductivity type as that of a source and drain regions and connects thereto, thereby enabling the potential of the select gate to be almost fixed at a desired value, preventing a faulty operation and making it possible to cause the select transistor to operate at high speed.

Claims

1. A nonvolatile semiconductor memory device comprising:

a semiconductor substrate with a main surface;

a plurality of memory cell units formed on said main surface of said semiconductor substrate, each of said memory cell units having a plurality of memory cells connected in one unit, each of said memory cells containing

a first charge accumulation layer formed on said main surface of said semiconductor substrate in an insulating manner,

a first control gate formed on said first charge accumulation layer in an insulating manner, and

two first diffusion layers formed at said main surface of said semiconductor substrate on both side of said first charge accumulation layer, at least one of said two first diffusion layers being shared by adjacent one of said memory cells, thereby connecting said memory cells adjacent to each other;

a plurality of first select transistors connected to one end of each of said plurality of memory cell units via one of said first diffusion layers located at the one end,

each of said plurality of first select transistors containing a second control gate and a source and a drain region and being connected in series by adjacent one of said first select transistors sharing one of said source and said drain region, said second control gate being connected to each of a plurality of select gate lines,

at least one of said plurality of first select transistors further containing

a second charge accumulation layer on said main surface of said semiconductor substrate and under said second control gate in an insulating manner; and

a data line connected to at least two adjacent ones of said memory cell units via said plurality of first select transistors.

2. A nonvolatile semiconductor memory device according to claim 1, wherein at least another one of said plurality of first select transistors includes a third charge accumulation layer electrically connected to said second control gate.

3. A nonvolatile semiconductor memory device according to claim 1, wherein at least one of said first select transistors in which said second charge accumulation layer and said second control gate are stacked in an insulating manner, further contains a second diffusion layer that is formed at said main surface of said substrate under said second charge accumulation layer and is of a same conductivity type as that of said source and said drain region and connected thereto, thereby forming a depletion-mode transistor.

4. A nonvolatile semiconductor memory device according to claim 1, wherein said plurality of first select transistors include a depletion-mode transistor and an enhancement-mode transistor.

5. A nonvolatile semiconductor memory device according to claim 1, wherein two of said memory cell units are coupled with said data line, one memory cell unit being connected to said data line via said first select transistors in which a first depletion-mode transistor and a first enhancement-mode transistor are connected in series, and another one of said memory cell units being connected to said data line via said first select transistors in which a second enhancement-mode transistor and a second depletion-mode transistor are connected in series.

6. A nonvolatile semiconductor memory device according to claim 5, wherein said first depletion-mode transistor and said second enhancement-mode transistor are connected to one of said select gate lines, and said second depletion-mode transistor and said first enhancement-mode transistor are connected to another one of said select gate lines.

7. A nonvolatile semiconductor memory device according to claim 1, wherein another end of each of said plurality of memory cell units which is unconnected to said data line is connected to a reference voltage line via at least one second select transistor.

8. Non-volatile semiconductor memory device according to claim 1, wherein each of said memory cell units includes said plurarity of memory cells connected in series along said data line.

9. Non-volatile semiconductor memory device according to claim 1, wherein each of said memory cell units includes said plurarity of memory cells connected in parallel along said data line.

10. Non-volatile semiconductor memory device according to a claim 1, wherein said first charge accumulation layer is formed of a same layer as said second charge accumulation layer of said first select transistor.

11. Non-volatile semiconductor memory device according to a claim 1, wherein said first control gate of each of said memory cells is formed of a same layer as said second control gate of each of said first select transistors.

12. A nonvolatile semiconductor memory device comprising:

a semiconductor substrate with a main surface;

a plurality of memory cell units formed on said main surface of said semiconductor substrate, each of said memory cell units having a plurality of memory cells connected in one unit, each of said memory cells containing

a first charge accumulation layer formed on said main surface of said semiconductor substrate in an insulating manner,

a first control gate formed on said charge accumulation layer in an insulating manner, and

two first diffusion layers formed at said main surface of said semiconductor substrate on both side of said charge accumulation layer, at least one of said first diffusion layers being shared by adjacent one of said memory cells, thereby connecting said memory cells adjacent to each other;

a plurality of first select transistors connected to one end of each of said plurality of memory cell units via one of said diffusion layers located at the one end,

each of said plurality of first select transistors containing

a gate insulating film formed on said main surface of said semiconductor substrate,

a second control gate formed on said gate insulating film, and

a source and a drain region formed at said main surface of said semiconductor substrate on both side of said second control gate, at least one of said source and said drain region being shared by adjacent one of said select transistors and connecting said adjacent one of said select transistors in series, said second control gate being connected to a corresponding one of a plurality of control gate lines, and said gate insulating film of at least one of said first select transistors being made thicker than said gate insulating film of another one of said first select transistors; and

a data line connected to at least two adjacent ones of said memory cell units via said plurality of first select transistors.

13. A nonvolatile semiconductor memory device according to claim 12, wherein at least one of said first select transistors in which said first gate insulating film is made thicker than that of another one of said first select transistors, further contains a second diffusion layer that is formed at said main surface of said substrate under said first charge accumulation layer and is of a same conductivity type as that of said source and said drain region and connected thereto, thereby forming a depletion-mode transistor.

14. A nonvolatile semiconductor memory device according to claim 12, wherein said plurality of first select transistors include a depletion-mode transistor and an enhancement-mode transistor.

15. A nonvolatile semiconductor memory device according to claim 12, wherein two of said memory cell units are coupled with said data line, one memory cell unit being connected to said data line via said first select transistors in which a first depletion-mode transistor and a first enhancement-mode transistor are connected in series, and another one of said first memory cell units being connected to said data line via said first select transistors in which a second enhancement-mode transistor and a second depletion-mode transistor are connected in series.

16. A nonvolatile semiconductor memory device according to claim 15, wherein said first depletion-mode transistor and said second enhancement-mode transistor are connected to one of said select gate lines, and said second depletion-mode transistor and said first enhancement-mode transistor are connected to another one of said select gate lines.

17. A nonvolatile semiconductor memory device according to claim 12, wherein another end of each of said plurality of memory cell units which is unconnected to said data line is connected to a reference voltage line via at least one second select transistor.

18. A nonvolatile semiconductor memory device according to claim 12, wherein at least one of said plurality of first select transistors further contains a second charge accumulation layer on said main surface of said semiconductor substrate and under said second control gate in an insulating manner.

19. A nonvolatile semiconductor memory device comprising:

a semiconductor substrate with a main surface;

a plurality of memory cell units formed on said main surface of said semiconductor substrate, each of said memory cell units having a plurality of memory cells connected in one unit, each of said memory cells containing

a first charge accumulation layer formed on said main surface of said semiconductor substrate in an insulating manner,

a first control gate formed on said charge accumulation layer in an insulating manner, and

two first diffusion layers formed at said main surface of said semiconductor substrate on both side of said charge accumulation layer, at least one of said two first diffusion layers being shared by adjacent one of said memory cells, thereby connecting said memory cells adjacent to each other;

a plurality of first select transistors connected to one end of each of said plurality of memory cell units via one of said diffusion layers located at the one end,

each of said plurality of first select transistors containing

a second control gate formed on said main surface of said semiconductor substrate in an insulating manner, and

a source and a drain region formed at said main surface of said semiconductor substrate on both side of said second control gate, at least one of said source and said drain region being shared by adjacent one of said first select transistors and connecting said adjacent one of said memory cells in series, said second control gate being connected to a corresponding one of a plurality of control gate lines, and

at least one of said plurality of first select transistors having a second diffusion layer of a same conductivity type as that of said source and said drain region in said semiconductor substrate, said second diffusion layer being electrically connected to said source and said drain region; and

a data line connected to at least two adjacent ones of said memory cell units via said plurality of first select transistors.

20. A nonvolatile semiconductor memory device according to claim 19, wherein at least one of said plurality of first select transistors further contains a second charge accumulation layer on said main surface of said semiconductor substrate and under said second control gate in an insulating manner.

21. A nonvolatile semiconductor memory device according to claim 19, wherein at least one of said plurality of first select transistors contains a layer of a conductivity type opposite to that of said source and said drain region formed at said main surface of said substrate under said second control gate, and thereunder is formed said second diffusion layer that is of the same conductivity type of that of said source and said drain region and connected thereto.

22. A nonvolatile semiconductor memory device according to claim 19, wherein said plurality of first select transistors include a depletion-mode transistor and an enhancement-mode transistor.

23. A nonvolatile semiconductor memory device according to claim 19, wherein two of said memory cell units are coupled with said data line, one memory cell unit being connected to said data line via said first select transistors in which a first depletion-mode transistor and a first enhancement-mode transistor are connected in series, and another one of said memory cell units being connected to said data line via said first select transistors in which a second enhancement-mode transistor and a second depletion-mode transistor are connected in series.

24. A nonvolatile semiconductor memory device according to claim 23, wherein said first depletion-mode transistor and said second enhancement-mode transistor are connected to one of said select gate lines, and said second depletion-mode transistor and said first enhancement-mode transistor are connected to another one of said select gate lines.

25. A nonvolatile semiconductor memory device according to claim 19, wherein another end of each of said plurality of memory cell units which is unconnected to said data line is connected to a reference voltage line via at least one second select transistor.