High gain, low offset input amplifier
First Claim
1. An input signal amplifier comprising:
- a first operational amplifier;
a biasing amplifier comprising a second operational amplifier;
first and second voltage divider resistors coupled in series for connection across a DC bias voltage, a first input terminal of said second operational amplifier coupled to a first node between said first and second voltage divider resistors;
a feedback loop coupling an output of said second operational amplifier to a second input terminal of said second operational amplifier;
third and fourth voltage divider resistors coupled in series, said third resistor being coupled to said output of said second operational amplifier, a first input terminal of said first operational amplifier coupled to a second node between said third and fourth voltage divider resistors for receiving a fixed bias voltage; and
a second input terminal of said first operational amplifier coupled to receive an input signal and, in response thereto, to generate an output signal Vout.
1 Assignment
0 Petitions
Accused Products
Abstract
An input signal buffer amplifier that has a high gain and a low offset voltage is implemented as an integrated circuit (IC) along with other components that perform further processing on an input signal. In one embodiment, the buffer amplifier includes first and second operational amplifiers (op amps). Voltage divider resistors R1 and R2 are connected in series between a positive voltage supply rail and a ground rail of the IC. The positive input terminal of the second op amp is electrically connected to a node between resistors R1 and R2. A feedback loop is established from the output of the second op amp to its negative terminal. The negative terminal of the first op amp is connected to a node between a series-connected input resistor and feedback resistor. The positive input terminal of the first op amp is connected to a node between series-connected voltage divider resistors R3 and R4 which are connected across the output of the second op amp and the ground rail. The first operational amplifier generates an output voltage signal VI+ and the second operational amplifier generates an output voltage signal VI-.
10 Citations
7 Claims
-
1. An input signal amplifier comprising:
-
a first operational amplifier; a biasing amplifier comprising a second operational amplifier; first and second voltage divider resistors coupled in series for connection across a DC bias voltage, a first input terminal of said second operational amplifier coupled to a first node between said first and second voltage divider resistors; a feedback loop coupling an output of said second operational amplifier to a second input terminal of said second operational amplifier; third and fourth voltage divider resistors coupled in series, said third resistor being coupled to said output of said second operational amplifier, a first input terminal of said first operational amplifier coupled to a second node between said third and fourth voltage divider resistors for receiving a fixed bias voltage; and a second input terminal of said first operational amplifier coupled to receive an input signal and, in response thereto, to generate an output signal Vout. - View Dependent Claims (2, 3, 4)
-
-
5. An input signal amplifier for amplifying an input signal VIN to provide an output signal VID, said input signal amplifier comprising:
-
a first operational amplifier configured to produce a first output voltage signal VI+; a second operational amplifier configured to produce a second output voltage signal VI-; said output signal VID comprising the difference between the absolute values of VI+ and VI- and being equal to;
##EQU8## first and second voltage divider resistors coupled in series, a first input terminal of said second operational amplifier coupled to a first node between said first and second voltage divider resistors;third and fourth voltage divider resistors coupled in series, said third resistor being coupled to an output of said second operational amplifier, a first input terminal of said first operational amplifier coupled to a second node between said third and fourth voltage divider resistors; a feedback resistor having a resistance RF coupled between an output of said first operational amplifier and a second input terminal of said first operational amplifier; an input resistor having a resistance RI, said feedback resistor RF being coupled in series with said input resistor having a resistance RI ; and a second input terminal of said first operational amplifier coupled to receive a voltage signal and, in response thereto, to generate said first output signal VI+. - View Dependent Claims (6, 7)
-
Specification