Linear amplifier

• US 5,699,014 A
• Filed: 04/04/1996
• Issued: 12/16/1997
• Est. Priority Date: 04/04/1996
• Status: Expired due to Term

• Current Assignee: Cardiac Pacemakers Incorporated (Boston Scientific Corporation)
• Original Assignee: Cardiac Pacemakers Incorporated (Boston Scientific Corporation)
• Inventors: Linder, William J., Haefner, Paul A.
• Primary Examiner(s): MOTTOLA, STEVEN J
• Application Number:
  US08/627,403
• Time in Patent Office: 621 Days
• Field of Search: 128/696, 330/253, 330/256, 330/261
• US Class Current: 330/253
• CPC Class Codes: H03F 1/3205 in field-effect transistor amplifiers
• CPC Class Codes: H03F 1/3211 in differential amplifiers
• CPC Class Codes: H03F 2200/162 FETs are biased in the weak inversion region
• CPC Class Codes: H03F 2200/372 Noise reduction and elimination in amplifier

Abstract

A low-noise, low-power complementary metal-oxide-semiconductor (CMOS) integrated circuit common source differential amplifier is disclosed which is capable of amplifying low amplitude cardiac signals such as those produced by atrial depolarization of the heart. The amplifier has a pair of large area p-channel input field-effect transistors (FETs) biased in weak inversion. The amplifier also has active load FETs biased in the nonsaturation (linear) region by means of a varying gate terminal voltage applied by a dynamic bias circuit. The gate terminal voltage is varied to match the temperature dependence of the output conductance of the load FETs to the temperature dependence of the transconductance of the input FETs. The gate terminal voltage also sets a dc bias point which uses the nonlinearity in the load FET output conductance to cancel nonlinearity in the input FET transconductance.

Claims

1. An integrated circuit amplifier comprising:

a differential pair of input field-effect transistors (FETs) receiving a differential input voltage signal having a first input signal component and a second input signal component and providing in response thereto a differential output voltage signal having a first output signal component and a second output signal component, the differential pair of input FETs including;

a first input FET having a source terminal, a gate terminal receiving the first input signal component, and a drain terminal providing the first output signal component, and

a second input FET having a source terminal coupled to the source terminal of the first input FET, a gate terminal receiving the second input signal component, and a drain terminal providing the second output signal component;

a first load FET having a source terminal, a gate terminal, a drain terminal coupled to the drain terminal of the first input FET, and a controlled conductance between the drain terminal and the source terminal;

a second load FET having a source terminal coupled to the source terminal of the first load FET, a gate terminal coupled to the gate terminal of the first load FET, a drain terminal coupled to the drain terminal of the second input FET, and a controlled conductance between the drain terminal and the source terminal; and

a dynamic bias circuit coupled to the gate terminals of the first and second load FET for keeping the first load FET and the second load FET in a nonsaturation region and for controlling the conductance between the drain terminal and the source terminal of each of the first and second load FETs by applying a varying bias voltage to the gate terminals of each of the first and second load FETs.

2. The amplifier of claim 1, wherein each input FET comprises a p-channel metal-oxide-semiconductor (PMOS) FET.

3. The amplifier of claim 1, wherein electronic noise contributed by the first and second load FETs is substantially negligible relative to electronic noise contributed by the first and second input FETs.

4. The amplifier of claim 1, wherein the input FETs are biased in a weak inversion region of operation.

5. The amplifier of claim 1, wherein the differential output voltage signal represents an approximate linear amplification of the differential input voltage signal for the differential input voltage signal of up to a selected differential input voltage signal magnitude.

6. The amplifier of claim 5, wherein the selected differential input voltage signal magnitude is approximately 30 mV.

7. The amplifier of claim 1, wherein the amplifier provides an approximately temperature independent voltage gain from the differential input voltage signal to the differential output voltage signal.

8. The amplifier of claim 1, wherein the amplifier is capable of providing an approximately temperature independent voltage gain from the differential input voltage signal to the differential output voltage signal of approximately 8.3.

9. The amplifier of claim 1, wherein the controlled load conductance between the drain terminal and the source terminal of each of the first and second load FETs has a temperature dependence which is closely matched to a temperature dependence of the corresponding differential input FET to which the drain terminal of the load FET is coupled.

10. The amplifier of claim 1, wherein the controlled conductance between the drain terminal and the source terminal of each of the first and second load FETs has a bias current dependence which is closely matched to a bias current dependence of a transconductance of the corresponding differential input FET to which the drain terminal of the load FET is coupled.

11. The amplifier of claim 1, wherein nonlinearity in differential transconductance of the differential input FETs is reduced by nonlinearity in the controlled conductance between the drain terminal and the source terminal of the first and second load FETs.

12. The amplifier of claim 1, wherein the dynamic bias circuit comprises:

a replicate FET having a source terminal coupled to the source terminals of the first and second load FETs, a gate terminal coupled to the gate terminals of each of the first and second load FETs, and a drain terminal, wherein a proportional to absolute temperature (PTAT) current is received at the drain terminal of the replicate FET and the replicate FET is operated in the nonsaturation region; and

a PTAT voltage generator circuit for coupling a PTAT voltage between the drain terminal and the source terminal of the replicate FET and for applying a biasing voltage at the gate terminal of the replicate FET, wherein the biasing voltage at the gate terminal of the replicate FET is provided to the gate terminal of each of the first and second load FETs.

13. The amplifier of claim 12, wherein the replicate FET of the dynamic bias circuit is closely matched to each of the first and the second load FETs.

14. The amplifier of claim 1, where the dynamic bias circuit comprises:

a first replicate FET having a source terminal coupled to the source terminal of each of the first and second load FETs, a gate terminal coupled to the gate terminal of each of the first and second load FETs, and a drain terminal, wherein a PTAT current is received at the drain terminal of the first replicate FET, and the first replicate FET is operated in the nonsaturation region;

a second replicate FET having a source terminal coupled to the source terminal of each of the first and second load FETs, a gate terminal coupled to the gate terminal of each of the first and second load FETs and coupled to the gate terminal of the first replicate FET, and a drain terminal, wherein a PTAT current is received at the drain terminal of the second replicate FET, and wherein the PTAT current received at the drain terminal of the second replicate FET differs in magnitude from the PTAT current received at the drain terminal of the first replicate FET, and the second replicate FET is operated in the nonsaturation region; and

a PTAT voltage generator circuit for applying a differential PTAT voltage between the drain terminal of the first replicate FET and the drain terminal of the second replicate FET and applying a biasing voltage at the gate terminal of the first replicate FET and the gate terminal of the second replicate FET coupled thereto, wherein the biasing voltage at the gate terminal of the first replicate FET and the gate terminal of the second replicate FET coupled thereto is provided to the gate terminal of the load FETs.

15. The amplifier of claim 14, wherein the first replicate FET and the second replicate FET are closely matched to each load FET.

16. A method of signal amplification using a differential amplifier including first and second differential input FETs coupled at common source terminals, each of the first and second differential input FETs having a gate terminal, the differential amplifier further including first and second load field-effect transistors (FETs) coupled at common gate terminals and common source terminals, the first and second load FETs each having a drain terminal coupled to a corresponding drain terminal of first and second input FETs respectively, the method comprising the steps of:

receiving a differential input voltage signal between the gate terminals of each of the first and second input FETs;

amplifying the differential input voltage signal by a linear amplification voltage gain resulting in a differential output voltage signal, the linear amplification voltage gain varying with temperature according to a temperature sensitivity; and

biasing the common gate terminals of the first and second load FETs with a varying bias voltage to reduce the temperature sensitivity of the linear amplification voltage gain.

17. The method of claim 16, wherein the step of receiving the differential input voltage signal between the gate terminals of each of the first and second input FETs is performed by PMOS input FETs.

18. The method of claim 16, further comprising the step of biasing the input FETs in a weak inversion region.

19. The method of claim 16, wherein the step of biasing the common gate terminals of the first and second load FETs includes the step of biasing the load FETs in a nonsaturation region.

20. The method of claim 16, wherein the amplifier further comprises a biasing network having a replicate FET which duplicates the first and second load FETs, and wherein the step of biasing the common gate terminals of the first and second load FETs with a varying bias voltage includes the steps of:

biasing the replicate FET in the nonsaturation region;

receiving a proportional to absolute temperature (PTAT) voltage between a drain terminal and a source terminal of the replicate FET;

receiving a PTAT bias current at the drain terminal of the replicate FET; and

forming a resulting biasing voltage output at a gate terminal of the replicate FET to provide the varying input bias voltage at the common gate terminals of the first and second load FETs.

21. The method of claim 16, wherein the amplifier further comprises a biasing network having first and second replicate FETs duplicating the first and second load FETs, and wherein the first and second replicate FETs have common gate terminals coupled to the common gate terminals of the first and second load FETs, and wherein the step of biasing the common gate terminals of the first and second load FETs with a varying bias voltage includes the steps of:

biasing the first and second replicate FETs in the nonsaturation region;

applying a differential proportional to absolute temperature (PTAT) voltage between a drain terminal of the first replicate FET and a drain terminal of the second replicate FET;

receiving a first PTAT current at the drain terminal of the first replicate FET;

receiving at the drain terminal of the second replicate FET a second PTAT current of different magnitude than the first PTAT current; and

forming a resulting biasing voltage output at the common gate terminals of the first and second replicate FETs to provide the varying bias voltage at the common gate terminals of the first and second load FETs.

22. A cardiac rhythm management system, comprising:

at least one sensing electrode for sensing electrical depolarization signals produced by a heart;

an amplifier having first and second input ports coupled to the sensing electrode and receiving the sensed electrical depolarization signals as a differential input voltage signal between the first and second input ports, the differential input voltage signal having a first input signal component at the first input port and a second input signal component at the second input port, and the amplifier providing in response thereto a differential output voltage signal having a first output signal component and a second output signal component, the amplifier comprising;

a first input field-effect transistor (FET) having a source terminal, a gate terminal coupled to the first input port and receiving the first input signal component, and a drain terminal providing the first output signal component;

a second input FET having a source terminal coupled to the source terminal of the first input FET, a gate terminal receiving the second input signal component, and a drain terminal providing the second output signal component;

a first load FET having a source terminal, a gate terminal, a drain terminal coupled to the drain terminal of the first input FET, and a controlled conductance between the drain terminal and the source terminal;

a second load FET having a source terminal coupled to the source terminal of the first load FET, a gate terminal coupled to the gate terminal of the first load FET, a drain terminal coupled to the drain terminal of the second input FET, and a controlled conductance between the drain terminal and the source terminal; and

a dynamic bias circuit coupled to the gate terminals of the first and second load FETs for keeping the first load FET and the second load FET in a nonsaturation region and for controlling the conductance between the drain terminal and the source terminal of each of the first and second load FETs by applying a varying bias voltage to the gate terminals of each of the first and second load FETs.

23. The cardiac rhythm management system of claim 22, wherein the sensed electrical depolarization signals produced by the heart include electrical depolarization signals produced by an atrial chamber of the heart.

24. The cardiac rhythm management system of claim 22, wherein the cardiac rhythm management system is capable of being implanted in either a human or animal.