Display device

• US 5,699,085 A
• Filed: 12/02/1992
• Issued: 12/16/1997
• Est. Priority Date: 12/03/1991
• Status: Expired due to Term

• Current Assignee: ROHM Co., Ltd.
• Original Assignee: ROHM Co., Ltd.
• Inventors: Takei, Toshikazu, Saito, Masao
• Primary Examiner(s): Hjerpe, Richard
• Assistant Examiner(s): LAO, LUNYI
• Application Number:
  US07/984,674
• Time in Patent Office: 1,840 Days
• Field of Search: 340/762, 340/782, 340/811, 340/813, 340/799, 340/798, 340/750, 345/46, 345/82, 345/211, 345/212, 345/213, 345/185, 345/196, 345/197, 345/204
• US Class Current: 345/531
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: G09G 3/32 semiconductive, e.g. using light-emitting diodes [LED]
• CPC Class Codes: G09G 5/395 Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen G09G5/399 takes precedence

Abstract

The display device includes a plurality of display elements to be driven selectively or simultaneously; a storage unit for storing display data to be displayed by the display elements; a storage control unit for generating a display inhibition signal for a predetermined period of time from turning-on of a power supply till the display data of the storage unit is made definite; and a display driving control unit for breaking supply of a driving current to the display elements when the storage control unit is generating the display inhibition signal.

Claims

1. A display device, comprising:

a plurality of display elements to be driven selectively or simultaneously;

storage means for storing display data to be displayed by said display elements;

a storage control means for generating a display inhibition signal for a predetermined period of time from turning-on of a power supply till said display data of said storage means is made definite; and

a display driving control means for breaking supply of a driving current to said display elements when said storage control means is generating said display inhibition signal.

2. A display device as claimed in claim 1, wherein said display driving control means includes a clock detection circuit, an AND circuit and a pre-driver, said clock detection circuit outputting to said AND circuit a clock detection signal indicating presence of a clock signal, said AND circuit receiving said display inhibition signal, said clock detection signal and a control signal indicating whether display operation is performed, and said pre-driver receiving a signal from said AND circuit to control a driving current supplied to said display elements.

3. A display device, comprising:

a plurality of display elements to be driven selectively or simultaneously;

a common signal generating means for generating a plurality of different common signals to establish current conduction periods of driving currents to be supplied to said display elements respectively; and

a clock frequency converting means provided in a stage before said common signal generating means and supplied with a clock signal, for converting a frequency of said clock signal in response to an external clock selection signal and for supplying said frequency converted clock signal to said common signal generating means.

4. A display device as claimed in claim 3, wherein said clock frequency converting means includes a divider and a first decoder, said divider receiving said clock signal to produce a plurality of frequency converted clock signals havaing different frequencies from each other, and said first decoder extracting one of said frequency converted clock signals.

5. A display device as claimed in claim 4, wherein said divider is constituted by an inverter and a plurality of flip-flops, and said first decoder is constituted by a gate circuit receiving said external clock selection signal, a plurality of NAND circuits connected to said gate circuit and said divider, and a NOR circuit receiving outputs of said NAND circuit and outputting said one of said frequency converted clock signals.

6. A display device as claimed in claim 4, wherein said common signal generating means includes a counter receiving said extracted one of said frequency converted clock signals, and a second decoder for decording a count value of said couter to produce said common signals corresponding to said one of said frequency converted clock signals.

7. A display device as claimed in claim 3, further including clock selection signal generating means to supply an external clock selection signal to the clock frequency converting means to convert the frequency of the clock signal provided thereby.