Semiconductor circuit design verifying apparatus
First Claim
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1. A semiconductor circuit design verifying apparatus comprising:
- design information inputting means for inputting design information of a semiconductor circuit, the semiconductor circuit including a plurality of active devices and a plurality of signal lines;
parasitic device retrieving means for retrieving a parasitic device for a signal line, the signal line connecting a plurality of first stage active devices to a next stage active device driven by the first stage active devices, based on the design information input by said design information inputting means, each active device and the parasitic device including a resistance component and a capacitance component;
time constant computing means for computing a time constant between each first stage active device and the next stage active device driven by each first stage active device, among the plurality of active devices, each time constant being calculated from the resistance and capacitance components of each first stage active device, the next stage active device, and the parasitic device for the signal line connecting the first stage active devices and the next stage active device retrieved by the parasitic device retrieving means; and
time constant information outputting means for displaying each time constant and information associated with each time constant computed by the time constant computing means in connection with at least a part of the design information of the semiconductor circuit.
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Abstract
In a semiconductor circuit design verifying apparatus, a parasitic device retrieving part retrieves a parasitic device for a signal line connecting first stage active devices to a next stage active device. A time constant computing device computes a time constant between each first stage active device and the next stage active device including the parasitic device for the signal line between the first stage active devices and the next stage active device. An output data generating device outputs the time constant and information associated with the time constant to a user.
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11 Claims
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1. A semiconductor circuit design verifying apparatus comprising:
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design information inputting means for inputting design information of a semiconductor circuit, the semiconductor circuit including a plurality of active devices and a plurality of signal lines; parasitic device retrieving means for retrieving a parasitic device for a signal line, the signal line connecting a plurality of first stage active devices to a next stage active device driven by the first stage active devices, based on the design information input by said design information inputting means, each active device and the parasitic device including a resistance component and a capacitance component; time constant computing means for computing a time constant between each first stage active device and the next stage active device driven by each first stage active device, among the plurality of active devices, each time constant being calculated from the resistance and capacitance components of each first stage active device, the next stage active device, and the parasitic device for the signal line connecting the first stage active devices and the next stage active device retrieved by the parasitic device retrieving means; and time constant information outputting means for displaying each time constant and information associated with each time constant computed by the time constant computing means in connection with at least a part of the design information of the semiconductor circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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Specification