Failure detection system for a mirrored memory dual controller disk storage system

• US 5,699,510 A
• Filed: 05/30/1996
• Issued: 12/16/1997
• Est. Priority Date: 12/15/1994
• Status: Expired due to Term

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Company (HP Inc.)
• Inventors: Oldfield, Barry J., Petersen, Mark D.
• Primary Examiner(s): Nguyen, Hoa T.
• Assistant Examiner(s): Palys, Joseph E.
• Application Number:
  US08/657,714
• Time in Patent Office: 565 Days
• Field of Search: 395/183.13, 395/183.18, 395/182.04, 395/182.05, 395/182.07, 395/185.01, 395/185.07
• US Class Current: 714/54
• CPC Class Codes: G06F 11/0757 by exceeding a time limit, i.e. time-out, e.g. watchdogs
• CPC Class Codes: G06F 11/1612 where the redundant component is persistent storage
• CPC Class Codes: G06F 11/1633 using mutual exchange of the output between the redundant processing components
• CPC Class Codes: G06F 11/1666 where the redundant component is memory or memory area
• CPC Class Codes: G06F 11/20 using active fault-masking, e.g. by switching out faulty elements or by switching in spare elements
• CPC Class Codes: G06F 11/2089 Redundant storage control functionality
• CPC Class Codes: G06F 11/2097 maintaining the standby controller/processing unit updated initialisation or re-synchronisation thereof G06F11/1658 and subgroups
• CPC Class Codes: G06F 11/28 by checking the correct order of processing G06F11/08 - G06F11/26 take precedence; monitoring patterns of pulse trains H03K5/19
• CPC Class Codes: G11C 29/74 using duplex memories, i.e. using dual copies

Abstract

In a disk storage system having dual controllers and mirrored memory therebetween, arbitration logic associated with each controller generates state transition signals to identify the mirrored memory access status for the controller generating the signal. Each arbitration logic also monitors the state transition signals of the other. A failure in the mirrored memory system between the dual controllers is detected by one controller sensing an incorrect state transition signal communicated from the other controller. A failure is also detected by one controller not sensing a state transition signal from the other within a specified timeout period. Memory refresh cycles are tapped to cause the arbitration logic to cycle through state transition signals thereby forcing each controller to attempt a mirrored memory access on a regular basis whereby a memory system failure may be detected.

Claims

1. A failure detection system for a computer disk storage control system having a plurality of controllers, comprising:

(a) real-time mirrored memory on each controller with respect to each other controller;

(b) means for communicating a first state transition signal by a first controller of the plurality of controllers to a second controller of the plurality of controllers at least upon each event of a memory refresh cycle of the first controller, wherein the first state transition signal identifies a mirrored memory access status of the first controller;

(c) means for timing a predetermined interval of time in connection with and beginning concurrently with the communication of the first state transition signal from the first controller to the second controller; and

,

(d) means for sensing one of;

(i) a second state transition signal communicated from the second controller to the first controller in response to the first state transition signal, wherein the second state transition signal identifies a valid mirrored memory access status or a failure of the second controller; and

,

(ii) a completion of the interval of time indicative of a failure of the second controller.

2. The failure detection system of claim 1 wherein the first state transition signal is a signal indicative of a request for access to the mirrored memory of each controller.

3. The failure detection system of claim 1 further comprising means for communicating the first state transition signal upon an event of a memory access cycle.

5. The failure detection system of claim 1 wherein the second state transition signal is an incorrect state transition signal relative to what the first controller expects in response to the first state transition signal communicated, whereby failure of the second controller is detected by the first controller due to the incorrect state transition signal.

6. The failure detection system of claim 1 wherein the second state transition signal is communicated from the second controller to the first controller upon sensing the first state transition signal.

7. The failure detection system of claim 1 wherein the state transition signals include signals indicative of a local controller memory access status, selected from the group consisting of:

(a) being a slave, wherein access to the memory is disallowed;

(b) requesting access to the memory;

(c) being a master, wherein access to the memory is allowed;

(d) granting memory access to a remote controller;

(e) failing to being granted access to the memory by a remote controller;

(f) resetting its circuitry;

(g) resynchronizing its circuitry with a remote controller; and

,

(h) isolating communication from a remote controller.

8. The failure detection system of claim 1 further including control means on each controller for controlling access to the mirrored memory of the controller on which the control means resides, and wherein the control is based on the state transition signals generated.

9. The failure detection system of claim 8 wherein the control means includes a memory controller, buffers, and transceivers for enabling, disabling, and selecting flow direction of memory address and data signals.

4. The failure detection system of claim I wherein the second state transition signal is a signal indicative of a granting of access to the mirrored memory to the first controller, and whereby the second controller is denied access to the mirrored memory.

10. A method of detecting a memory system failure in a computer disk storage control system having first and second disk controllers and real-time mirrored memory therebetween, comprising the steps of:

(a) the first controller communicating a first state transition signal to the second controller at least upon each event of a memory refresh cycle of the first controller, wherein the first state transition signal identifies a mirrored memory access status of the first controller;

(b) the first controller starting a timer concurrently with the communication of the first state transition signal for timing a predetermined interval of time; and

,

(c) the first controller sensing one of;

(i) a second state transition signal communicated from the second controller to the first controller in response to the first state transition signal, wherein the second state transition signal identifies a valid mirrored memory access status or a failure of the second controller; and

,

(ii) a completion of the interval of time indicative of a failure of the second controller memory system.

11. The method according to claim 10 wherein the first state transition signal indicates a request for access to the mirrored memory.

12. The method according to claim 10 wherein the first state transition signal is communicated upon an event of a memory access cycle.

13. The method according to claim 10 wherein the second state transition signal grants access to the mirrored memory to the first controller, and whereby the second controller is denied access to the mirrored memory.

14. The method according to claim 10 wherein the second state transition signal is an incorrect state transition signal relative to what the first controller expects in response to the first state transition signal communicated, whereby failure of the second controller memory system is detected by the first controller due to the incorrect state transition signal.

15. The method according to claim 10 wherein the second state transition signal is communicated upon sensing the first state transition signal.

16. The method according to claim 10 wherein the state transition signals include signals indicative of a local controller memory access status, selected from the group consisting of:

(a) being a slave, wherein access to the memory is disallowed;

(b) requesting access to the memory;

(c) being a master, wherein access to the memory is allowed;

(d) granting memory access to a remote controller;

(e) failing to being granted access to the memory by a remote controller;

(f) resetting its circuitry;

(g) resynchronizing its circuitry with a remote controller; and

,

(h) isolating communication from a remote controller.

17. The method according to claim 10 further including the step of controlling access to the mirrored memory by the controller on which the memory resides based on the state transition signals generated.

18. The method according to claim 17 wherein the step of controlling access includes signaling a memory controller, buffers, and transceivers for enabling, disabling, and selecting flow direction of memory address and data signals.