Process for fabricating a semiconductor integrated circuit device

• US 5,700,704 A
• Filed: 06/02/1995
• Issued: 12/23/1997
• Est. Priority Date: 02/09/1990
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi, Ltd.
• Inventors: Meguro, Satoshi, Yamanaka, Toshiaki, Kobayashi, Yutaka, Hashimoto, Naotaka, Ikeda, Shuji, Ishibashi, Koichiro, Yukutake, Seigou, Hiraishi, Atsushi, Takahashi, Shigeru, Moriwaki, Nobuyuki, Koike, Atsuyoshi, Sasaki, Katsuro, Hashiba, Soichiro, Kuramoto, Isamu
• Primary Examiner(s): TSAI, H JEY
• Application Number:
  US08/458,615
• Time in Patent Office: 935 Days
• Field of Search: 437/919, 437/52, 437/193
• US Class Current: 438/96
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element
• CPC Class Codes: Y10S 257/903 FET configuration adapted for use as static memory cell
• CPC Class Codes: Y10S 257/904 with passive components,, e.g. polysilicon resistors

Abstract

A method is provided for manufacturing a semiconductor integrated circuit device which includes a capacitor element having a first electrode, a second electrode, and a dielectric film formed between said first electrode and said second electrode. In particular, the method includes the step of forming at least one of the first electrode and second electrode with a polycrystalline silicon film which is deposited over a semiconductor substrate by a CVD method and which is doped with an impurity during said deposition to decrease the resistance of the polycrystalline silicon film. The capacitor element formed by this method is particularly useful for memory cells of static random access memory devices.

Claims

1. A method of manufacturing a memory cell of a static random access memory, said memory cell including a driver MISFET and a capacitor element, said capacitor element having a first electrode, a second electrode, and a dielectric film between said first and said second electrode, said driver MISFET having a gate electrode serving as said first electrode of said capacitor element, said method comprising the steps of:

forming a polycrystalline silicon film over a semiconductor substrate by depositing the polycrystalline silicon film by a CVD method and doping the polycrystalline film with an impurity during the deposition to decrease the resistance and the surface roughness of said polycrystalline silicon film,

wherein said first electrode is formed of said polycrystalline silicon film,

wherein said second electrode is formed over an upper surface of said polycrystalline silicon film,

wherein said dielectric film is formed between said upper surface of said polycrystalline silicon film and a lower surface of said second electrode, and

wherein dielectric strength of the dielectric film is improved due to the reduced surface roughness of the polycrystalline silicon film.

2. A method of manufacturing a memory cell according to claim 1, wherein said polycrystalline silicon film is deposited by the CVD method using disilane as a source gas.

3. A method of manufacturing a memory cell according to claim 1, wherein a film thickness of said dielectric film is smaller than that of said first and said second electrode.

4. A method of manufacturing a memory cell according to claim 3, wherein said dielectric film is comprised of a silicon oxide film formed by the CVD method.

5. A method of manufacturing a memory cell according to claim 1, wherein said second electrode is comprised of another polycrystalline silicon film which is deposited by the CVD method and which is doped with an impurity during said deposition to decrease the resistance of said another polycrystalline silicon film.

6. A method of manufacturing a memory cell according to claim 5, wherein said dielectric film includes a silicon oxide film formed by the CVD method.

7. A method of manufacturing a semiconductor integrated circuit device, said semiconductor integrated circuit device comprising a memory cell including a first inverter circuit, a second inverter circuit, a first capacitor element, and a second capacitor element,

said first inverter circuit including a first driver MISFET and a first load element coupled in series,

said second inverter circuit including a second driver MISFET and a second load element coupled in series,

each of said first and said second capacitor elements including a first electrode, a second electrode, and a dielectric film formed between said first electrode and said second electrode,

said first electrode of said first capacitor element electrically connected to a drain region of said first driver MISFET and a gate electrode of said second driver MISFET,

said first electrode of said second capacitor element electrically connected to a drain region of said second driver MISFET and a gate electrode of said first driver MISFET,

said method comprising the step of:

forming one of said first electrode and said second electrode of said capacitor element by a polycrystalline silicon film by depositing the polycrystalline silicon film over a semiconductor substrate by a CVD method and doping the polycrystalline silicon film with an impurity during said deposition to decrease the resistance and the surface roughness of said polycrystalline silicon film, and

forming the other of said first electrode and said second electrode of said capacitor element over said semiconductor substrate by deposition;

wherein said dielectric film of said capacitor element is formed between a surface of said polycrystalline silicon film and a surface of said second electrode; and

wherein dielectric strength of the dielectric film is improved by the reduced surface roughness of the polycrystalline silicon film.

8. A method of manufacturing a semiconductor integrated circuit device according to claim 7, wherein said polycrystalline silicon film is deposited by the CVD method using disilane as a source gas.

9. A method of manufacturing a semiconductor integrated circuit device according to claim 7, wherein said first load element and said second load element are a first load MISFET and a second load MISFET, respectively, wherein a gate electrode of said first load MISFET is integrally formed with said first electrode of said second capacitor element, wherein a gate electrode of said second load MISFET is integrally formed with said first electrode of said first capacitor element, and wherein said first electrode of said capacitor element is formed of said polycrystalline silicon film.

10. A method of manufacturing a semiconductor integrated circuit device according to claim 9, wherein said gate electrodes of said load MISFETs are formed over said gate electrodes of said driver MISFETs.

11. A method of manufacturing a semiconductor integrated circuit device according to claim 10, wherein said gate electrode of said driver MISFET is made of a polycrystalline silicon film which is deposited over a semiconductor substrate by a CVD method and which is doped with an impurity during said deposition to decrease the resistance of said polycrystalline silicon film.

12. A method of manufacturing a semiconductor integrated circuit device according to claim 11, wherein said drain region and a source region of said driver MISFET are formed in said semiconductor substrate, wherein a wiring line extends over parts of said gate electrodes of said driver MISFETs and is electrically connected to said source regions of said driver MISFETs, and wherein said gate electrodes of said load MISFETs extend over said wiring line and are formed over said driver MISFETs.

13. A method of manufacturing a semiconductor integrated circuit device according to claim 7, wherein said dielectric film includes a silicon oxide film formed by the CVD method.

14. A method of manufacturing a semiconductor integrated circuit device according to claim 7, wherein said first electrode is comprised of said polycrystalline silicon film, and wherein said second electrode is comprised of another polycrystalline silicon film which is deposited by the CVD method and which is doped with an impurity during said deposition to decrease the resistance of said another polycrystalline silicon film.

15. A method of manufacturing a semiconductor integrated circuit device according to claim 7, further comprising the steps of:

forming said gate electrode of said driver MISFET by a polycrystalline silicon film which is deposited over a semiconductor substrate by the CVD method and which is doped with an impurity during said deposition to decrease the resistance of said polycrystalline silicon film; and

forming a word line which extends over a part of said gate electrodes of said driver MISFETs,

wherein said memory cell further includes a first and a second transfer MISFET each having a gate electrode which is coupled to said word line.

16. A method of manufacturing 1 semiconductor integrated circuit device according to claim 15, wherein a film thickness of a gate insulating film of transfer MISFET is greater than a film thickness of a gate insulating film of driver MISFET.

17. A method of manufacturing a semiconductor integrated circuit device according to claim 15, said word line forming step comprising substeps of:

forming a first insulating film over said semiconductor substrate;

depositing a first conductive layer over said first insulating film;

forming openings in both said first conductive layer and said first insulating film by etching both said first conductive layer and said first insulating film;

after said opening forming step, depositing a second conductive layer over said first conductive layer; and

patterning both said second conductive layer and said first conductive layer to form said word line and a wiring line,

said wiring line being electrically connected to source regions of said driver MISFETs through said openings.

18. A method of manufacturing a semiconductor integrated circuit device according to claim 17, wherein said first conductive layer is comprised of a polycrystalline silicon film which is deposited by the CVD method and which is doped with an impurity during said deposition to decrease the resistance of said polycrystalline silicon film.

19. A method of manufacturing a semiconductor integrated circuit device according to claim 17, wherein said word line is integrally formed with said gate electrodes of said transfer MISFETs.

20. A method of manufacturing a semiconductor integrated circuit device according to claim 15, wherein a film thickness of said gate electrode of said driver MISFET is thinner than a film thickness of said word line.

21. A method of manufacturing a semiconductor integrated circuit device according to claim 20, wherein said word line comprises a polycrystalline silicon film and a silicide film formed thereon.

22. A method of manufacturing a semiconductor integrated circuit device according to claim 20, wherein said first load element and said second load element are a first load MISFET and a second load MISFET, respectively, wherein a gate electrode of said first load MISFET is integrally formed with said first electrode of said second capacitor element, wherein a gate electrode of said second load MISFET is integrally formed with said first electrode of said first capacitor element, and wherein gate electrodes of said load MISFETs are formed over said gate electrodes of said driver MISFETs.

23. A method of manufacturing a semiconductor integrated circuit device according to claim 22, wherein said first electrode of said capacitor element is formed of said polycrystalline silicon film.

24. A method of manufacturing a semiconductor integrated circuit device according to claim 7, wherein said second electrode is formed over said first electrode.

25. A method of manufacturing a semiconductor integrated circuit device according to claim 24, wherein said first electrode is comprised of said polycrystalline silicon film and is integrally formed with said gate electrode of said driver MISFET.