Lateral trench MISFET

• US 5,701,026 A
• Filed: 10/25/1995
• Issued: 12/23/1997
• Est. Priority Date: 10/25/1994
• Status: Expired due to Term

• Current Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Original Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Inventors: Fujishima, Naoto, Kitamura, Akio
• Primary Examiner(s): FAHMY, WAEL M
• Application Number:
  US08/547,910
• Time in Patent Office: 790 Days
• Field of Search: 257/330, 257/332, 257/334, 257/335, 257/336, 257/337, 257/343, 257/344, 257/374, 257/510
• US Class Current: 257/510
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7801 DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region lateral high-voltage MISFETs with channel well and drain offset region H01L29/7835
• CPC Class Codes: H01L 29/7809 having both source and drain contacts on the same surface, i.e. Up-Drain VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: Y10S 148/126 Power FETs
• CPC Class Codes: Y10S 148/151 Simultaneous diffusion

Abstract

To provide a lateral MISFET that has a uniform and reliable gate insulation film, and exhibits low on-resistance and excellent balance between the breakdown voltage and on-resistance. The device of the invention has an n-type semiconductor substrate, in a part of the surface layer thereof is formed a trench. An n-drain region is formed in the bottom of the trench. A side wall oxide film is formed on the side face of the trench. The trench is filled with a conductive material, on which is formed a drain electrode. A p-base region and an n-source region are self-aligned on the portion of the substrate in which the trench is not formed. A MIS gate is disposed on the p-base region. Since the portion of the substrate along the side wall oxide film functions as a drain drift region, the unit cell dimension are greatly reduced, the on-resistance is reduced, and therefore the trade-off relation between the breakdown voltage and the on-resistance is improved.

Claims

1. A lateral trench MISFET comprising:

a semiconductor layer of a first conductivity type;

a trench formed in a surface layer of said semiconductor layer;

a drain region of the first conductivity type formed at a bottom of said trench;

a side wall insulation film formed on a side face of said trench;

a base region of a second conductivity type formed in a portion of said semiconductor layer separate from the trench;

a source region of the first conductivity type formed in a part of a surface layer of said base region, such that said base region forms an extension portion that extends between said semiconductor layer and said source region;

a gate electrode overlying said extension portion;

a gate insulation film provided between the gate electrode and said extension portion;

a source electrode connected to both said source region and said base region; and

a conductive material disposed in said trench.

2. The lateral trench MISFET according to claim 1, further comprising a side wall region of the second conductivity type formed in said semiconductor layer along said side wall insulation film of said trench.

3. The lateral trench MISFET according to claim 1, further comprising a semiconductor substrate of the second conductivity type disposed beneath said semiconductor layer.

4. The lateral trench MISFET according to claim 1, wherein said gate electrode extends to an outside edge of the side wall insulation film.

5. The lateral trench MISFET according to claim 1, further comprising a drain electrode disposed on said conductive material.

6. A lateral trench MISFET comprising:

a semiconductor layer of a first conductivity type;

a trench formed in a surface layer of said semiconductor layer;

a drain region of the first conductivity type formed at a bottom of said trench;

a side wall insulation film formed on a side face of said trench;

a well region of the first conductivity type formed in a part of the surface layer of said semiconductor layer separate from the trench, said well region being more heavily doped than said semiconductor layer;

a base region of a second conductivity type formed in a part of a surface layer of said well region;

a source region of the first conductivity type formed in a surface layer of said base region, such that said base region forms an extension portion that extends between said well region and said source region;

a gate electrode overlying said extension portion;

a gate insulation film provided between the gate electrode and said extension portion;

a source electrode connected to both said source region and said base region; and

a conductive material disposed in said trench.

7. The lateral trench MISFET according to claim 6, further comprising a side wall region of the second conductivity type formed in said semiconductor layer along said side wall insulation film of said trench.

8. The lateral trench MISFET according to claim 6, further comprising a semiconductor substrate of the second conductivity type disposed beneath said semiconductor layer.

9. The lateral trench MISFET according to claim 6, wherein said gate electrode extends to an outer side of said trench.

10. The lateral trench MISFET according to claim 6, further comprising a drain electrode disposed on said conductive material.

11. A lateral trench MISFET comprising:

a semiconductor layer of a first conductivity type;

a trench formed in a surface layer of said semiconductor layer;

a drain drift region of a second conductivity type formed at a portion of said semiconductor layer facing said trench;

a drain region of the second conductivity type formed at a bottom of said trench, said drain region being more heavily doped than said drain drift region;

a side wall insulation film formed on a side face of said trench;

a base region of the first conductivity type formed in a portion of said semiconductor layer separate from the trench;

a source region of the second conductivity type formed in a part of a surface layer of said base region, such that said base region forms an extension portion that extends between said drain drift region and said source region;

a gate electrode overlying the extension portion;

a gate insulation film provided between the gate electrode and said extension portion

a source electrode connected to both said source region and said base region; and

a conductive material disposed in said trench.

12. The lateral trench MISFET according to claim 11, further comprising a side wall region of the first conductivity type formed in said drain drift region along said side wall insulation film.

13. The lateral trench MISFET according to claim 11, further comprising a drain electrode disposed on said conductive material.

14. A lateral trench MISFET comprising:

a semiconductor layer of a first conductivity type;

a trench formed in a surface layer of said semiconductor layer;

a drain region of the first conductivity type formed at a bottom of said trench;

a side wall insulation film formed on a side face of said trench;

a base region of a second conductivity type formed at least in a part of the surface layer of said semiconductor layer separate from said trench;

a source region of the first conductivity type formed in a part of a surface layer of said base region, said base region including a trench facing portion between said semiconductor layer and said source region;

a gate electrode opposed to and facing the trench portion of said base region;

a gate insulation film provided between said gate electrode and said trench facing portion;

a source electrode connected to both said source region and said base region; and

a conductive material disposed in said trench.

15. The lateral trench MISFET according to claim 14, further comprising a semiconductor substrate of the second conductivity type disposed beneath said semiconductor layer.

16. The lateral trench MISFET according to claim 14, further comprising a drain electrode disposed on said conductive material.

17. A lateral trench MISFET comprising:

a semiconductor layer of a first conductivity type;

a trench formed in a surface layer of said semiconductor layer;

a drain region of the first conductivity formed at a bottom of said trench;

a side wall insulation film formed on a side face of said trench;

a well region of the first conductivity type formed at least in a part of the surface layer of said semiconductor layer separate from the trench, said well region being more heavily doped than said semiconductor layer;

a base region of a second conductivity type formed in a part of a surface layer of said well region;

a source region of the first conductivity type formed in a part of a surface layer of said base region, said base region including a trench facing portion that extends between said well region and said source region;

a gate electrode opposed to and facing the trench facing portion of said base region;

a gate insulation film provided between said gate electrode and said trench facing portion;

a source electrode connected to both said source region and said base region; and

a conductive material disposed in said trench, said conductive material being from said gate electrode.

18. The lateral trench MISFET according to claim 17, further comprising a semiconductor substrate of the second conductivity type disposed beneath said semiconductor layer.

19. The lateral trench MISFET according to claim 17, further comprising a drain electrode disposed on said conductive material.

20. A lateral trench MISFET comprising:

a semiconductor layer of a first conductivity type;

a trench formed in a surface layer of said semiconductor layer;

a drain drift region of a second conductivity type formed in a portion of said semiconductor layer facing said trench;

a drain region of the second conductivity type formed at a bottom of said trench, said drain region being more heavily doped than said drain drift region;

a side wall insulation film formed on a side face of said trench;

a base region of the first conductivity type formed at least in a part of the surface layer of said semiconductor layer separate from said trench;

a source region of the second conductivity type formed in a part of a surface layer of said base region, said base region including a trench facing portion between said drain drift region and said source region;

a gate electrode opposed to and facing the trench facing portion of said base region;

a gate insulation film provided between said gate electrode and said trench portion;

a source electrode connected to both said source region and said base region; and

a conductive material disposed in said trench, said conductive material being insulated from said gate electrode.

21. The lateral trench MISFET according to claim 20, further comprising a drain electrode disposed on said conductive material.