Circuits, systems and methods for improving row select speed in a row select memory device

• US 5,701,143 A
• Filed: 01/31/1995
• Issued: 12/23/1997
• Est. Priority Date: 01/31/1995
• Status: Expired due to Term

• Current Assignee: Intellectual Ventures II LLC (Intellectual Ventures LLC)
• Original Assignee: Cirrus Logic Incorporated
• Inventors: Rao, G. R. Mohan
• Primary Examiner(s): Powell, Mark R.
• Assistant Examiner(s): Kovalick, Vincent E.
• Application Number:
  US08/381,189
• Time in Patent Office: 1,057 Days
• Field of Search: 345/185, 345/196, 345/201, 395/427, 395/410, 395/438, 395/404, 365/230.03, 365/230.06
• US Class Current: 345/545
• CPC Class Codes: G11C 8/10 Decoders

Abstract

A memory device 200 is provided which includes an array 202 of rows and columns of memory cells 201. Row decoder circuitry 206 is provided for selecting a given row of cells 201 for access. Circuitry 208, 209 is included for providing a selected one of a plurality of supply voltages to the row decoder circuitry 206, a first positive voltage provided during an active state of the row decoder circuitry 206 and a second positive voltage provided during an inactive state of the row decoder circuitry 206.

Claims

1. A memory device comprising:

an array of rows and columns of memory cells, each said row associated with a conductive wordline;

row decoder circuitry coupled to each said wordline for selecting a said row of cells for access; and

circuitry for providing a selected one of a plurality of supply voltages to said row decoder circuitry, said circuitry providing a first positive voltage during an active state of said decoder circuitry and providing a second positive voltage during an inactive state of said decoder circuitry.

2. The memory device of claim 1 wherein said array of cells comprises an array of dynamic random access memory cells.

3. The memory device of claim 1 wherein said second voltage is derived from said first voltage.

4. The memory device of claim 3 wherein said second voltage is derived from said first voltage using a resistor voltage divider.

5. The memory device of claim 3 wherein said second voltage is derived from said first voltage using a voltage divider constructed of field effect transistors.

6. A memory device operating in response to a predetermined device supply voltage comprising:

an array of rows and columns of memory cells;

a row decoder for accessing a selected one of said row of cells, said row decoder circuitry active during an active period of a row address strobe and inactive during an inactive period of said row address strobe;

DC to DC converter circuitry operable to generate a power-down supply voltage from said device supply voltage; and

circuitry for providing said device supply voltage to said row decoder during said active period and said power-down supply voltage to said row decoder from said converter circuitry during said inactive period.

7. The memory device of claim 6 wherein said DC to DC converter circuitry includes a resistor voltage divider.

8. The memory device of claim 6 wherein said DC to DC converter includes a voltage divider constructed of field effect transistors.

9. The memory device of claim 6 wherein said circuitry for providing includes a transistor for switching said power-down voltage from said converter circuitry to said decoder in response to a power-down control signal, said power-down control signal having an active period substantially equal to said inactive period of said row address strobe.

10. The memory device of claim 6 wherein said circuitry for providing includes a transistor for switching said supply voltage to said decoder in response to an active state control signal, said active state control signal having a period substantially equal to said active period of said row address strobe.

11. A data processing system comprising:

a controller;

a memory bank comprising an array of rows and columns of memory cells and row decoder circuitry for selecting a said row of cells for access; and

circuitry for providing a selected one of a plurality of supply voltages to said row decoder circuitry, said circuitry for providing a first positive voltage in anticipation of a selection by said decoder circuity of a row in the array for access and providing a second positive voltage during an inactive state of said decoder circuitry following access to the selected row.

12. The processing system of claim 11 wherein said controller comprises a display controller and said memory system comprises a frame buffer system.

13. The processing system of claim 11 wherein:

said processing system further comprises a second memory bank including a second array of rows and columns of memory cells and second row decoder circuitry for selecting a said row of cells in said array for access; and

said circuitry for providing further provides said first positive voltage to said second decoder circuitry in anticipation of a row selection by said second decoder circuitry and said second positive voltage to said second decoder circuitry during an inactive period of said second decoder circuitry.

14. The processing system of claim 11 wherein said controller and said memory system are integrated on a single chip.

15. The processing system of claim 11 wherein said array of memory cells comprises an array of dynamic random access memory cells.

16. A method of operating a memory device including an array of rows and columns of memory cells and row decoder circuitry for accessing the cells of a selected one of the rows, the method comprising the steps of:

providing a first positive supply voltage to the decoder circuitry during an active state of the decoder circuitry; and

providing a second positive supply voltage to the decoder circuitry during an inactive state of the decoder circuitry.

17. The method of claim 16 and further comprising the step of generating the second voltage from the first voltage.

18. The method of claim 17 wherein said step of generating comprises a step of generating the second voltage from the first voltage using a DC to DC conversion technique.

19. A method of operating a memory system including a first memory bank including an array of rows and columns of memory cells and an associated row decoder and a second memory bank including an array of rows and columns of memory cells and an associated row decoder, the method comprising the steps of:

providing the decoder of the first bank with a full supply voltage in anticipation of selecting a row in the array of the first bank for access;

providing the decoder of the first bank with a power-down supply voltage following access to the selected row in the array of the first bank;

providing the decoder of the second bank with the full supply voltage in anticipation of selecting a row in the array of the second bank for access; and

providing the decoder of the second bank with the power-down supply voltage following access to the selected row in the array of the second bank.

20. The method of claim 19 and further comprising the step of generating the power-down supply voltage from the full supply voltage.