Single chip controller-memory device with interbank cell replacement capability and a memory architecture and methods suitble for implementing the same
DCFirst Claim
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1. A memory subsystem comprising:
- processing circuitry;
first and second banks of memory, each said bank including a predetermined number of primary memory cells and a predetermined number of redundant memory cells;
a primary address bus for allowing said processing circuitry to address at least one of said primary memory cells, said at least one primary memory cell residing in a primary cell memory space; and
a redundancy bus for allowing said processing circuitry to address at least one of said redundancy cells, said at least one redundancy cell residing in a redundacy cell memory space separate from said primary cell memory space.
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Abstract
A memory subsystem 300 including processing circuitry 103 and first and second banks of memory 200/201. Each bank 200/201 includes a predetermined number of primary memory cells 200 and a predetermined number of redundant memory cells 205. An address bus 202 allows processing circuitry 103 to address at least one of the primary cells 200. The redundancy bus 301 allows processing circuitry 103 to address at least one of the redundancy cells 205.
80 Citations
26 Claims
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1. A memory subsystem comprising:
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processing circuitry; first and second banks of memory, each said bank including a predetermined number of primary memory cells and a predetermined number of redundant memory cells; a primary address bus for allowing said processing circuitry to address at least one of said primary memory cells, said at least one primary memory cell residing in a primary cell memory space; and a redundancy bus for allowing said processing circuitry to address at least one of said redundancy cells, said at least one redundancy cell residing in a redundacy cell memory space separate from said primary cell memory space. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A memory device comprising:
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information processing circuitry; a plurality of arrays of rows and columns of memory cells, each said array including a preselected number of primary rows and columns and a preselected number of redundant rows and columns; first address logic for individually addressing said primary rows and columns of cells in response to bits presented by said processing circuitry on a primary address bus, said bits presented on said primary address bus defining a primary address space in which said primary rows and columns reside; second address logic for individually addressing said redundant rows and columns in response to bits presented by said processing circuitry on a redundancy bus, said bits presented on said redundancy bus defining a redundancy address space in which said redundant rows and columns reside. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
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20. A processing system comprising:
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a controller; a redundancy bus; a memory comprising; a plurality of memory banks each comprising an array of memory cells, each said array including a preselected number of primary cells and a preselected number of redundant memory cells; circuitry for preventing access to defective ones of said primary cells of a first selected one of said banks; and address decoding circuitry for accessing selected ones of said redundant cells in a second selected one of said banks in response to a redundancy address presented by said controller on said redundancy bus said redundancy address including a plurality of primary row/column address bits and at least one redundancy address bit; and wherein said controller is operable to generate said redundancy address to access said selected redundant cells in response to need to access said defective primary cells. - View Dependent Claims (21, 22, 23, 24)
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25. A method of replacing defective memory cells in a system including a controller and a multi-bank memory device, the memory comprising the steps of:
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identifying a defective set of memory cells in a first one of the banks, the defective memory cells associated with a bank select bit and a location address bit and addressable by the controller via a primary address bus; programming a redundant set of memory cells in a second one of the banks, the redundant set of cells addressable with a bank select bit, a primary location address bit, and a redundancy address bit by the controller via a redundancy address bus; and addressing the redundant set of cells via the redundancy bus in response to a need by the controller to access the defective set of cells. - View Dependent Claims (26)
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Specification