Fast bist architecture with flexible standard interface
First Claim
1. A circuit for testing one or more integrated circuits, each integrated circuit having main logic circuitry operating according to a system clock signal supplied from an external source, the circuit comprising:
- a source of input test data;
one or more scan registers for receiving the input test data according to a test clock signal, supplying the input test data to the main logic circuitry, receiving output test data generated by the main logic circuitry in response to the input test data, and shifting the output test data according to the test clock signal;
a test data signature element for receiving the output test data and forming a test data signature from the output test data; and
a clock multiplexer, located external to the one or more integrated circuits, for selectively replacing the system clock signal from the external source with the test clock signal such that the scan registers receive the input test data, and shift the output test data while the system clock signal is replaced.
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Accused Products
Abstract
A built-in self test architecture for testing one or more integrated circuits. Each circuit is provided with an interface compatible with IEEE standard 1149.1 and one or more scan registers containing scan cells for supplying input test data to, and receiving output test data from, the internal circuitry of the integrated circuits, a pseudo-random pattern generator for supplying patterns of test data to the boundary scan register, and a pattern compressor for compressing the output test data into a signature. The architecture also includes a single clock multiplexer, located external to the integrated circuits, for selectively supplying a system clock or a test clock to the testing components of each integrated circuit.
109 Citations
22 Claims
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1. A circuit for testing one or more integrated circuits, each integrated circuit having main logic circuitry operating according to a system clock signal supplied from an external source, the circuit comprising:
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a source of input test data; one or more scan registers for receiving the input test data according to a test clock signal, supplying the input test data to the main logic circuitry, receiving output test data generated by the main logic circuitry in response to the input test data, and shifting the output test data according to the test clock signal; a test data signature element for receiving the output test data and forming a test data signature from the output test data; and a clock multiplexer, located external to the one or more integrated circuits, for selectively replacing the system clock signal from the external source with the test clock signal such that the scan registers receive the input test data, and shift the output test data while the system clock signal is replaced. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method for testing the logic circuitry of one or more integrated circuits, the internal circuitry operating according to a system clock signal supplied from an external source, comprising:
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generating input test data from an input data source; interrupting the supply of the system clock signal to each of the one or more integrated circuits at a point external to each of the one or more integrated circuits; sampling and storing the input test data in one or more scan registers connected to the logic circuitry of each of the one or more integrated circuits according to a test clock signal supplied from an external source, each scan register having a number of scan cells; supplying the system clock signal to the integrated circuits; supplying the input test data to the logic circuitry, the logic circuitry generating output test data in response to the input test data according to the system clock signal; interrupting the supply of the system clock signal; sampling the output test data and storing the sampled output test data in the scan registers according to the test clock signal; shifting the output test data stored in the scan registers according to the test clock signal; supplying the system clock signal to the integrated circuits; forming a data signature from the shifted output test data according to the system clock signal; comparing the data signature with a predetermined signature to generate an output test signal; interrupting the supply of the system clock signal; and outputting the output test signal from each integrated circuit according to the test clock signal. - View Dependent Claims (12, 13, 14)
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15. An integrated circuit arrangement, comprising:
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main logic circuitry operating according to an interruptable system clock signal supplied from an external source; an input test data source; one or more boundary scan registers for receiving input test data from the input test data source, supplying the input test data to the main logic circuitry, and receiving and storing output test data generated by the main logic circuitry in response to the input test data, each boundary scan register including a number of serially-connected boundary scan cells for sampling the input test data or the output test data and shifting sampled data to a connected boundary scan cell or to an output line, each boundary scan cell connected to a data pin of an integrated circuit and operating according to a test clock signal, the system clock signal being interrupted during the sampling and shifting of data by the boundary scan cells; one or more internal scan registers for receiving input test data from the input test data source, supplying the input test data to the main logic circuitry, and receiving and storing output test data generated by the main logic circuitry in response to the input test data, each boundary scan register including a number of serially-connected internal scan cells for sampling the input test data or the output test data and shifting sampled data to a connected internal scan cell or to the output line, each internal scan cell connected to an internal circuit element of an integrated circuit and operating according to the system clock signal; a data signature element for receiving the output test data stored in the boundary scan registers or the internal scan registers on the output line, forming a data signature, and comparing the data signature with a predetermined signature for determining the presence of faults in the integrated circuit; and an interface including a state machine for receiving a test control signal from an external source and generating instructions in response to the test control signal, an instruction register for storing the instructions, and an instruction decoder for decoding the instructions to control the sampling and shifting of data by the boundary scan cells and the internal scan cells. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22)
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Specification