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Fast bist architecture with flexible standard interface

  • US 5,701,308 A
  • Filed: 10/29/1996
  • Issued: 12/23/1997
  • Est. Priority Date: 10/29/1996
  • Status: Expired due to Term
First Claim
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1. A circuit for testing one or more integrated circuits, each integrated circuit having main logic circuitry operating according to a system clock signal supplied from an external source, the circuit comprising:

  • a source of input test data;

    one or more scan registers for receiving the input test data according to a test clock signal, supplying the input test data to the main logic circuitry, receiving output test data generated by the main logic circuitry in response to the input test data, and shifting the output test data according to the test clock signal;

    a test data signature element for receiving the output test data and forming a test data signature from the output test data; and

    a clock multiplexer, located external to the one or more integrated circuits, for selectively replacing the system clock signal from the external source with the test clock signal such that the scan registers receive the input test data, and shift the output test data while the system clock signal is replaced.

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