Error generation circuit for testing a digital bus

• US 5,701,409 A
• Filed: 02/22/1995
• Issued: 12/23/1997
• Est. Priority Date: 02/22/1995
• Status: Expired due to Term

• Current Assignee: PMC-Sierra Incorporated (Microchip Technology Incorporated)
• Original Assignee: Adaptec Incorporated (Steel Partners Holdings LP)
• Inventors: Gates, Stillman F.
• Primary Examiner(s): Beausoliel, Jr., Robert W.
• Assistant Examiner(s): Palys, Joseph E.
• Application Number:
  US08/392,442
• Time in Patent Office: 1,035 Days
• Field of Search: 395/183.19, 395/185.09, 395/183.06, 395/183.07, 395/183.17, 395/182.02
• US Class Current: 714/41
• CPC Class Codes: G06F 11/221 to test buses, lines or interfaces, e.g. stuck-at or open line faults
• CPC Class Codes: G06F 11/261 by simulating additional hardware, e.g. fault simulation

Abstract

In order to test a parallel digital bus, an integrated circuit adapted for coupling to the bus has a bus error generation circuit which generates and/or simulates bus error conditions on the bus. During test, an error command is loaded into a command register of the bus error generation circuit via the bus. The bus error generation circuit then decodes the command, and either: 1) generates an error condition on the bus during a subsequent bus cycle, or 2) simulates an error condition on the bus during a subsequent bus cycle. A status configuration register in the integrated circuit and status configuration registers in other devices on the bus are then read to determine whether the integrated circuit and other devices properly detected and/or handled the generated or simulated error. By providing a bus error generation circuit in the integrated circuits coupled to a bus inside personal computer, built-in test of the personal computer is facilitated.

Claims

1. A method, comprising the steps of:

(a) controlling an integrated circuit of a first device to generate a bus error condition onto a parallel bus;

(b) on a second device coupled to said parallel bus, detecting said bus error condition and asserting a signal on said bus indicative of said bus error condition;

(c) receiving said signal on said integrated circuit and setting a bit in a status register of said integrated circuit to log said bus error condition; and

(d) repeating said steps (a) through (c), wherein each of said steps (a) involves outputting a different data value onto said parallel bus and outputting an incorrect parity value onto said parallel bus for the different data value, the incorrect parity value during the first step (a) being different from the incorrect parity value output during the second step (a).

2. An integrated circuit, comprising:

a first plurality of address and data terminals for coupling to address and data lines of a PCI bus;

a parity generator having a plurality of input leads coupled to the first plurality of address and data terminals;

a second terminal for coupling to a PAR line of the PCI bus;

a third terminal for coupling to a PERR# line of the PCI bus;

a bus error generation circuit having a first input lead coupled to an output lead of the parity generator, the bus error generation circuit having a first output lead and a second input lead coupled the second terminal, the bus error generation circuit having a third input lead coupled to the third terminal, the bus error generation circuit also having a second plurality of output leads coupled to the plurality of input leads of the parity generator and to the first plurality of address and data terminals, the bus error generation circuit being capable of inverting a parity value received from the parity generator and outputting an inverted parity value on the second terminal; and

a register having a plurality of output leads, the plurality of output leads being coupled to a second plurality of input leads of the bus error generation circuit so that information stored in the register can pass through the bus error generation circuit and to the first plurality of address and data terminals,

wherein the bus error generation circuit comprises;

means for inverting a value received on the second terminal; and

a parity error check circuit outputting an error signal onto the third terminal if a parity determined for information received on the first plurality of address and data terminals differs from a value received from the means for inverting.

3. The integrated circuit of claim 2, wherein the bus error generation circuit further comprises:

a command register; and

a command decoder,

wherein the means for inverting has a first input lead, a second input lead, and an output lead, the first input lead being coupled to the second terminal, the second input lead being coupled to an output lead of the command decoder, the output lead being coupled to an input lead of the parity error check circuit.

4. The integrated circuit of claim 3, wherein the bus error generation circuit further comprises:

means for inverting a parity value received from the parity generator, the means for inverting a parity value having a first input lead, a second input lead and an output lead, the first input lead being coupled to the output lead of the parity generator, the second input lead being coupled to an output lead of the command decoder; and

an output register having an input lead and an output lead, the input lead being coupled to an output lead of the means for inverting a parity value, the output lead being coupled to the second terminal.