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Scalable system interrupt structure for a multi-processing system

  • US 5,701,495 A
  • Filed: 12/18/1995
  • Issued: 12/23/1997
  • Est. Priority Date: 09/20/1993
  • Status: Expired due to Fees
First Claim
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1. A system for processing interrupt requests within a data processing system having a plurality of processors and a plurality of interrupt sources, wherein each of said interrupt requests is associated with a priority and each of said plurality of processors is associated with a variable priority, said system comprising:

  • a software-accessible interrupt presentation layer including a plurality of queues for storing interrupt requests, wherein each of said plurality of queues is associated with a respective one of said plurality of processors, and wherein interrupt requests within each queue among said plurality of queues are only handled by a respective associated processor among said plurality of processors;

    a hardware routing means for routing an interrupt request issued by a particular one of said plurality of interrupt sources to a particular queue among said plurality of queues that is associated with a particular processor among said plurality of processors; and

    means for preventing priority inversion, wherein said means for preventing priority inversion removes said interrupt request from said particular queue in response to said interrupt request having a lower priority than said variable priority of said particular processor when another interrupt request having a higher priority than said variable priority of said particular processor is received by said particular queue and said particular queue is full.

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