Scalable system interrupt structure for a multi-processing system

• US 5,701,495 A
• Filed: 12/18/1995
• Issued: 12/23/1997
• Est. Priority Date: 09/20/1993
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Youngs, Amy May, Thurber, Steven Mark, Arndt, Richard Louis, Silha, Edward John, Nicholson, James Otto
• Primary Examiner(s): Harvey, Jack B.
• Assistant Examiner(s): WILEY, DAVID ARMAND
• Application Number:
  US08/573,918
• Time in Patent Office: 736 Days
• Field of Search: 395/736, 395/739, 395/741, 395/733, 395/734
• US Class Current: 710/263
• CPC Class Codes: G06F 9/4812 by interrupt, e.g. masked

Abstract

An interrupt subsystem within a data processing system is scalable from low-end uni-processor systems to high-end multi-processor (MP) systems. This interrupt subsystem provides for queueing of interrupts from many sources, and for queueing of interrupts to the best processor in a multi-processor system. The external interrupt mechanism is separated into two layers, an interrupt routing layer and an interrupt presentation layer. The interrupt routing layer routes the interrupt conditions to the appropriate instance of an interrupt management area within the interrupt presentation layer. The interrupt presentation layer communicates the interrupt source to the system software which is to service/process the interrupt. By providing two layers within the interrupt subsystem, application or system software can be written which is independent from the types or sources of interrupts. The interrupt routing layer hides the details of a particular hardware implementation from the software. The interrupt presentation layer interfaces to the system and/or application software, and provides hardware independent functionality.

Claims

1. A system for processing interrupt requests within a data processing system having a plurality of processors and a plurality of interrupt sources, wherein each of said interrupt requests is associated with a priority and each of said plurality of processors is associated with a variable priority, said system comprising:

a software-accessible interrupt presentation layer including a plurality of queues for storing interrupt requests, wherein each of said plurality of queues is associated with a respective one of said plurality of processors, and wherein interrupt requests within each queue among said plurality of queues are only handled by a respective associated processor among said plurality of processors;

a hardware routing means for routing an interrupt request issued by a particular one of said plurality of interrupt sources to a particular queue among said plurality of queues that is associated with a particular processor among said plurality of processors; and

means for preventing priority inversion, wherein said means for preventing priority inversion removes said interrupt request from said particular queue in response to said interrupt request having a lower priority than said variable priority of said particular processor when another interrupt request having a higher priority than said variable priority of said particular processor is received by said particular queue and said particular queue is full.

2. The system for processing interrupt requests of claim 1, wherein said hardware routing means routes said interrupt request to a best processor determined based upon a priority associated with said interrupt request and variable priorities associated with said plurality of processors.

3. The system for processing interrupts of claim 1, wherein said interrupt request presented to said particular processor includes a single source identifier that specifies which if said plurality of interrupt sources issued said interrupt request.

4. The system of claim 1, wherein

at least two of said plurality of processors are grouped into a of logical server;

said interrupt presentation layer includes a server queue associated with said logical server; and

said hardware routing means includes means for routing an interrupt request to said server queue and means for queuing said interrupt request within said server queue.

5. The system of claim 4, wherein:

said means for preventing priority inversion removes a selected interrupt request from said server queue in response to receipt of a second interrupt request at said server queue when said server queue is full, said second interrupt request having a higher priority than said selected interrupt request.

6. The system of claim 4, wherein said hardware routing means routes said interrupt request to a best processor within said logical server, said best processor determined based upon a priority associated with said interrupt request and variable priorities associated with processors within said logical server.

7. The system for processing interrupt requests of claim 1, wherein each of said plurality of interrupt sources comprises:

means for storing an interrupt request rejected by said means for routing; and

means for reissuing said interrupt request rejected by said means for routing.

8. The system for processing interrupt requests of claim 1, wherein said interrupt request is transmitted from said particular one of said plurality of interrupt sources to said means for routing via an address bus of said data processing system.

9. The system for processing interrupt requests of claim 1, wherein said plurality of interrupt sources includes said plurality of processors.

10. The system for processing interrupt requests within a data processing system of claim 1, wherein said particular queue associated with said particular processor is a logical queue comprising at least one queue of hardware-generated interrupts and one queue of software-generated interrupts.

11. The system for processing interrupt requests within a data processing system of claim 10, wherein said interrupt presentation layer presents only a most favored interrupt request selected from among said at least one queue of software-generated interrupt requests and at least one queue of hardware-generated interrupt requests.

12. The system of claim 1, wherein said hardware routing means includes means for rejecting said interrupt request if said particular queue is full and a priority associated with said interrupt request is lower than a priority associated with another interrupt request within said particular queue.

13. The system of claim 1, and further comprising software interrupt servicing means for servicing said interrupt request presented to said particular processor.

14. A method for processing interrupt requests within a data processing system having a plurality of processors and a plurality of interrupt sources, wherein each of said interrupt requests is associated with a priority and each of said plurality of processors is associated with a variable priority, said data processing system including a software-accessible interrupt presentation layer, said interrupt presentation layer includinq a plurality of queues for storing interrupt requests, wherein each of said plurality of queues is associated with a single one of said plurality of processors, said method comprising:

issuing a first interrupt request from a particular one of said plurality of interrupt sources;

routing said first interrupt request to a particular queue within said interrupt presentation layer that is associated with a particular processor among said plurality of processors;

queuing said first interrupt request within said particular queue associated with said particular processor, wherein only said particular processor handles interrupt requests within said particular queue; and

thereafter, removing said first interrupt request from said particular queue in response to receipt of a second interrupt request at said particular queue when said particular queue is full, said second interrupt request having a higher priority than said variable priority of said particular processor.

15. The method for processing interrupt requests of claim 14, wherein each of said plurality of processors is associated with a variable priority, and wherein said step of queuing said first interrupt request comprises queuing said first interrupt request for access by a best processor determined based upon a priority associated with said interrupt request and variable priorities associated with said plurality of processors.

16. The method of claim 14 said method comprising:

grouping at least two of said plurality of processors into a logical server; and

providing a server queue associated with said logical server within said interrupt presentation layer, wherein interrupt requests queued within said server queue may be accessed and serviced by any of said at least two processors within said logical server.

17. The method of claim 16, wherein said step of queuing said first interrupt request comprises queuing said first interrupt request for access by a best processor within said logical server, said best processor determined based upon a priority associated with said first interrupt request and variable priorities associated with those of said plurality of processors grouped within said logical server.

18. The method for processing interrupt requests of claim 14, and further comprising:

rejecting an interrupt request;

storing said rejected interrupt request issued by said particular interrupt source at said particular interrupt source; and

reissuing said rejected interrupt request.

19. The method for processing interrupt requests of claim 14, wherein said step of issuing a first interrupt request comprises transmitting said first interrupt request from said particular one of said plurality of interrupt sources to said particular queue via an address bus of said data processing system.

20. The method for processing interrupt requests of claim 14, wherein said step of issuing a first interrupt request from a particular one of said plurality of interrupt sources comprises issuing a first interrupt request from a particular one of said plurality of processors.

21. The method for processing interrupt requests within a data processing system of claim 14, wherein said particular queue associated with said particular processor is a logical queue comprising at least one queue of hardware-generated interrupts and one queue of software-generated interrupts, said method further comprising:

presenting an interrupt request queued within said particular queue associated with said particular processor to said particular processor for servicing.

22. The method for processing interrupt requests within a data processing system of claim 21 wherein said step of presenting an interrupt request comprises presenting only a most favored interrupt request selected from among said at least one queue of software-generated interrupt requests and at least one queue of hardware-generated interrupt requests.

23. The method of claim 14, and further comprising the step of rejecting said interrupt request without queuing said interrupt request if said particular queue is full and a priority associated with said interrupt request is lower than a priority associated with another interrupt request within said particular queue.

24. The method of claim 14, said method further comprising:

accessing said interrupt request within said particular queue utilizing interrupt servicing software executed by said particular processor; and

servicing said interrupt request accessed by said particular processor.

25. The method of claim 24, wherein said interrupt request accessed by said particular processor includes a single source identifier that specifies which of said plurality of interrupt sources issued said interrupt request.