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Method for manufacturing a stimulus wafer for use in a wafer-to-wafer testing system to test integrated circuits located on a product wafer

  • US 5,701,666 A
  • Filed: 04/16/1997
  • Issued: 12/30/1997
  • Est. Priority Date: 08/31/1994
  • Status: Expired due to Fees
First Claim
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1. A method for forming a stimulus wafer, the stimulus wafer being formed for stimulating a semiconductor product wafer, the method for forming the stimulus wafer comprising:

  • providing a substrate having a surface;

    forming, on the surface of the substrate in a first area, a plurality of input/output terminals coupled so that the input/output terminals provide test control signals external to the stimulus wafer;

    forming, on the surface of the substrate in a second area different from the first area, a plurality of integrated circuits wherein each integrated circuit in the plurality of integrated circuits contains test circuits coupled to top level conductive pads, the top level conductive pads being configured to allow the test circuits in the plurality of the integrated circuits to test product integrated circuits on the semiconductor product wafer via electrical test signals originating in the test circuits and transmitted through the top level conductive pads, the plurality of integrated circuits being laid out in a predetermined two-dimensional geometry across the surface of the substrate, the test circuits comprising circuitry for controlling voltage to the semiconductor product wafer, circuitry for controlling current to the semiconductor product wafer, and circuitry for controlling signals through the top level conductive pads to the semiconductor product wafer;

    forming at least one feedback circuit, on the surface of the substrate in a third area which is different from both the first and second area, the at least one feedback circuit comprising temperature monitoring circuitry and performance monitoring circuitry for identifying which circuits in the plurality of driver circuits have identified a stimulus problem on the semiconductor product wafer;

    forming a stimulus wafer conductive interconnect network for coupling signals between the plurality of input/output terminals, the plurality of driver circuits, and the at least one feedback circuit.

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