Method for manufacturing a stimulus wafer for use in a wafer-to-wafer testing system to test integrated circuits located on a product wafer

• US 5,701,666 A
• Filed: 04/16/1997
• Issued: 12/30/1997
• Est. Priority Date: 08/31/1994
• Status: Expired due to Fees

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: DeHaven, Robert Keith, Wenzel, James F.
• Primary Examiner(s): Vo, Peter
• Application Number:
  US08/843,491
• Time in Patent Office: 258 Days
• Field of Search: 29/407.01, 29/407.05, 29/830, 29/831, 29/832, 29/846, 29/850, 29/593, 324/754, 324/755, 324/758, 324/759, 437/8
• US Class Current: 29/831
• CPC Class Codes: G01R 1/07314 the body of the probe being perpendicular to test object, e.g. bed of nails or probe with bump contacts on a rigid support on an elastic support, e.g. a film, G01R1/0735
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00
• CPC Class Codes: G01R 31/2849 Environmental or reliability testing, e.g. burn-in or validation tests of individual semiconductors G01R31/2642; of printed circuits boards G01R31/2817; of IC's G01R31/2855
• CPC Class Codes: G01R 31/2863 Contacting devices, e.g. sockets, burn-in boards or mounting fixtures in general G01R1/04
• CPC Class Codes: G01R 31/2874 related to temperature
• CPC Class Codes: G01R 31/2879 related to electrical aspects, e.g. to voltage or current supply or stimuli or to electrical loads
• CPC Class Codes: G01R 31/2881 related to environmental aspects other than temperature, e.g. humidity or vibrations
• CPC Class Codes: Y10T 29/49004 including measuring or testing of device or component part
• CPC Class Codes: Y10T 29/49126 Assembling bases
• CPC Class Codes: Y10T 29/49128 Assembling formed circuit to base
• CPC Class Codes: Y10T 29/49155 Manufacturing circuit on or in base
• CPC Class Codes: Y10T 29/49162 by using wire as conductive path

Abstract

A method, apparatus, and circuit distribution wafer (CDW) (16) are used to wafer-level test a product wafer (14) containing one or more product integrated circuits (ICs). The CDW (16) contains circuitry which is used to test the ICs on the product wafers (14). A connection from the product wafer (14) to the CDW (16) is made via a compliant interconnect media (IM) (18). Through IM (18), the CDW (16) tests the product wafer (14) under any set of test conditions. Through external connectors and conductors (20, 22, 24, and 26) the CDW (16) transmits and receives test data, control information, temperature control, and the like from an external tester (104). To improve performance and testability, the CDW (16) and heating/cooling (80 and 82) of the wafers may be segmented into two or more wafer sections for greater control and more accurate testing.

Claims

1. A method for forming a stimulus wafer, the stimulus wafer being formed for stimulating a semiconductor product wafer, the method for forming the stimulus wafer comprising:

providing a substrate having a surface;

forming, on the surface of the substrate in a first area, a plurality of input/output terminals coupled so that the input/output terminals provide test control signals external to the stimulus wafer;

forming, on the surface of the substrate in a second area different from the first area, a plurality of integrated circuits wherein each integrated circuit in the plurality of integrated circuits contains test circuits coupled to top level conductive pads, the top level conductive pads being configured to allow the test circuits in the plurality of the integrated circuits to test product integrated circuits on the semiconductor product wafer via electrical test signals originating in the test circuits and transmitted through the top level conductive pads, the plurality of integrated circuits being laid out in a predetermined two-dimensional geometry across the surface of the substrate, the test circuits comprising circuitry for controlling voltage to the semiconductor product wafer, circuitry for controlling current to the semiconductor product wafer, and circuitry for controlling signals through the top level conductive pads to the semiconductor product wafer;

forming at least one feedback circuit, on the surface of the substrate in a third area which is different from both the first and second area, the at least one feedback circuit comprising temperature monitoring circuitry and performance monitoring circuitry for identifying which circuits in the plurality of driver circuits have identified a stimulus problem on the semiconductor product wafer;

forming a stimulus wafer conductive interconnect network for coupling signals between the plurality of input/output terminals, the plurality of driver circuits, and the at least one feedback circuit.

2. The method of claim 1 further comprising the step of:

forming a compliant interconnect region in contact with the top level conductive pads on a top portion of the stimulus wafer.

3. The method of claim 2 further comprising the step of:

placing a product wafer having integrated circuits onto the compliant interconnect region, the compliant interconnect region electrically coupling the stimulus wafer to the product wafer for testing of the product wafer via the integrated circuits of the stimulus wafer.

4. The method of claim 3 further comprising the step of:

testing the product wafer via signals transmitted from the stimulus wafer through the compliant interconnect region.

5. The method of claim 3 wherein the compliant interconnect region comprises elastomer material and conductive wires formed therethrough.

6. The method of claim 1 wherein the step of forming, on the substrate in a first area, the plurality of input/output terminals comprises:

forming a plurality of conduct-ire wires to the plurality of input/output terminals.

7. The method of claim 6 wherein the step of forming a plurality of conductive wires comprises:

forming a plurality of conductive wires to the plurality of input/output terminals by a process selected from a group consisting of;

spot bonding, gang bonding, ball bonding, soldering, and laser irradiation.

8. A method for forming a stimulus wafer, the stimulus wafer being formed for testing a semiconductor product wafer, the method for forming the stimulus wafer comprising:

providing a substrate having a surface;

patterning, on the surface of the substrate in a first area, a plurality of input/output terminals for communication of information external to the stimulus wafer;

coupling conductive wire to the plurality of input/output terminals for communication of the information external to the stimulus wafer, the conductive wire being coupled to the input/output terminals by a physical bonding technique;

forming, on the surface of the substrate in a second area different from the first area, a plurality of test circuits, the plurality of test circuits comprising circuitry for providing voltage, circuitry for monitoring current, and circuitry for driving test signals through upper level bond pads to enable testing of product circuits on another wafer, the test circuits being spatially configured into a two-dimensional layout of integrated circuits across the stimulus wafer where scribe lines separate the integrated circuits;

forming at least one feedback circuit, on the surface of the substrate in a third area which is different from both the first and second area, the at least one feedback circuit comprising circuitry for identifying which test circuits in the plurality of test circuits have identified a test problem in at least one product circuit on another wafer;

forming a stimulus wafer conductive interconnect network for coupling signals between at least two of the plurality of input/output terminals, the plurality of test circuits, and the at least one feedback circuit; and

forming an interconnect media overlying the plurality of test circuits wherein the interconnect media comprising an insulating portion and a plurality of conductive fibers through the insulating portion wherein the insulating portion separates each conductive fiber from all other conductive fibers, the plurality of conductive fibers being coupled to the circuitry for driving test signals within the plurality of test circuits for communicating the test signals to the products circuits of another wafer via the plurality of conductive fibers.

9. The method of claim 8 wherein the test circuits are formed provide a clock signal to the interconnect media.

10. The method of claim 8 wherein the test circuits are formed provide a reset signal to the interconnect media.

11. The method of claim 8 wherein the test circuits are formed provide a data input signal to the interconnect media and receive a data output signal from the interconnect media.

12. The method of claim 8 wherein the test circuits provide a data input signal to the interconnect media, a reset signal to the interconnect media, a clock signal to the interconnect media, and receive a data output signal from the interconnect media.

13. The method of claim 8 wherein the semiconductor product wafer is coupled to the interconnection media for testing wherein the semiconductor wafer is heating via a heating element placed in close proximity to the semiconductor product wafer.

14. The method of claim 8 wherein the stimulus wafer is heated by a heating element placed in dose proximity to the stimulus wafer.

15. A method for forming a stimulus wafer for testing product integrated circuits on a product wafer, the method comprising the steps of:

providing the stimulus wafer as a semiconductor wafer;

depositing a plurality of conductive layers and a plurality of dielectric layers on the stimulus wafer to form;

(1) a plurality of test integrated circuit die separated from each other by scribe lines and used for generating test signals to test another semiconductor wafer;

(2) at least one contact area coupled to at least one test integrated circuit die for communicating information to and from the at least one test integrated circuit die to an external tester to enable testing of another semiconductor wafer; and

(3) at least one feedback circuit wherein the at least one feedback circuit is coupled to the at least one contact area for communicating temperature information to the external tester, the plurality of test integrated circuit die having a top conductive layer of metal; and

forming a compliant interconnect media coupled to the top conductive layer of metal, the compliant interconnect media comprising dielectric material surrounding a plurality of conductive fibers wherein the conductive fibers couple to the top conductive layer of metal and provide electrical signals to test the integrated circuits on the product wafer.

16. The method of claim 15 wherein the top conductive layer of metal provides a clock signal, a reset signal, a test data input signal and a test data output signal to or from the compliant interconnect media.

17. The method of claim 15 wherein the stimulus wafer is divided into a plurality of segments, each segment containing many test integrated circuit die out of the plurality of test integrated circuit die and each segment containing one feedback circuit from the at least one feedback circuit wherein the one feedback circuit is coupled only to the many test integrated circuit die in the segment in which the one feedback circuit resides.

18. The method of claim 17 wherein each segment in the plurality of segments contains one contact area included in the at least one contact area.

19. The method of claim 17 further comprising the steps of:

manufacturing the product wafer having the product integrated circuits formed thereon wherein the product integrated circuits have a top conductive layer; and

coupling the top conductive layer of the product wafer to the plurality of conductive fibers of the compliant interconnect media to allow the stimulus wafer to test the product wafer via the compliant interconnect media.

20. The method of claim 15 wherein the at least one contact area has a plurality of conductive pads located at a top surface of the stimulus wafer wherein the plurality of conductive pads are electrically coupled to wires that coupled to a contactor device.