Method for forming a semiconductor device having a floating gate

• US 5,702,964 A
• Filed: 10/17/1995
• Issued: 12/30/1997
• Est. Priority Date: 10/17/1995
• Status: Expired due to Term

• Current Assignee: Magnachip Semiconductor Limited (Magnachip Semiconductor)
• Original Assignee: LG Semicon Co Ltd (SK Hynix Inc.)
• Inventors: Lee, Byung-Il
• Primary Examiner(s): Niebling, John
• Assistant Examiner(s): Booth, Richard A.
• Application Number:
  US08/544,317
• Time in Patent Office: 805 Days
• Field of Search: 437/43, 437/52
• US Class Current: 438/257
• CPC Class Codes: H10B 41/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 41/44 with a control gate layer also being used as part of the peripheral transistor

Abstract

A method for forming of a semiconductor device having a transistor with a floating gate includes the steps of forming a first insulating layer and a first conductive layer on a surface of the substrate, patterning the first conductive layer on a cell forming area to form preliminary floating gate electrodes and implanting ions on the cell forming area, forming a second insulating layer on the resulting surface so that the second insulating layer fills a space between the preliminary floating gate electrodes, forming a third insulating layer on the resulting surface, forming a second conductive layer on the third insulating layer, forming a fourth insulating layer on the second conductive layer, forming a gate electrode by patterning the fourth insulating layer and the second conductive layer, wherein the gate electrode pattern has a first distance between the gate lines in a portion to be a contact hole, and a second distance between the gate lines is arranged in another portion, the first distance being wider than the second distance, and forming a floating gate electrode by patterning the third insulating layer and the second conductive layer.

Claims

1. A method for forming of a semiconductor device including a transistor having a floating gate, comprising the steps of:

(a) forming a first insulating layer and a first conductive layer on a surface of the substrate;

(b) patterning the first conductive layer on a cell forming area for forming preliminary floating gate electrodes spaced by a distance and implanting ions on the cell forming area;

(c) forming a second insulating layer on the resulting surface formed after step (b) and etching the second insulating layer so that the second insulating layer remains on a side wall of the preliminary floating gate electrodes and fills the distance between preliminary floating gate electrodes;

(d) forming a third insulating layer on the resulting surface formed after step (c);

(e) forming a second conductive layer on the third insulating layer;

(f) forming a fourth insulating layer on the second conductive layer;

(g) forming gate electrode patterns by patterning the fourth insulating layer and the second conductive layer, wherein the gate electrode patterns have a first distance between the gate patterns in a portion to be a contact hole, and a second distance between the gate patterns is arranged in another portion, the first distance being wider than the second distance;

(h) forming a floating gate electrode by patterning the third insulating layer and the preliminary floating gate electrodes using the gate electrode patterns as a mask;

(i) forming source and drain regions by ion implantation;

(j) forming a fifth insulating layer and anisotropically etching the fifth insulating layer for forming a contact hole; and

(k) filling the contact hole with a third conductive layer, and patterning the third conductive layer into wiring.

2. The method according to claim 1, in step (c), a thickness of the second insulating layer is thicker than a half length of the distance between the preliminary floating gate electrodes.

3. The method according to claim 1, in step (j), the fifth insulating layer is deposited with a thickness which is greater than a half length of the second distance between the gate electrode patterns and less than a half length of the first distance between the gate electrode patterns.

4. The method according to claim 1, wherein the etching process in step (j) includes steps of forming a photoresist mask which covers a peripheral circuit portion except for the contact hole and does not cover the cell forming area, etching the fifth insulating layer until a portion of the fifth insulating layer on a horizontal surface is removed so that a portion of the fifth insulating layer remains on a side wall of the gate electrode patterns.

5. The method according to claim 1, wherein in step (b), the ion implanting is performed with a photoresist mask which covers a peripheral circuit portion.

6. The method according to claim 1, wherein the first through fifth insulating layers are at least each formed of one of silicon oxide and silicon nitride, and the first, second and third conductive layers are formed of polysilicon.

7. A method for forming of a semiconductor device including a transistor having a floating gate, comprising the steps of:

(a) forming a first insulating layer and a first conductive layer on a surface of the substrate;

(b) patterning the first conductive layer on a cell forming area to form preliminary floating gate electrodes spaced by a distance and implanting ions on the cell forming area;

(c) forming a second insulating layer on the resulting surface formed after step (b) so that the second insulating layer fills the distance between the preliminary floating gate electrodes;

(d) forming a third insulating layer on the resulting surface formed after step (c);

(e) forming a second conductive layer on the third insulating layer;

(f) forming a fourth insulating layer on the second conductive layer;

(g) forming gate electrode patterns by patterning the fourth insulating layer and the second conductive layer, wherein the gate electrode patterns have a first distance between the gate patterns in a portion to be a contact hole, and a second distance between the gate patterns is arranged in another portion, the first distance being wider than the second distance; and

(h) forming a floating gate electrode by patterning the third insulating layer and the preliminary floating gate electrodes.

8. The method according to claim 7, further comprising the steps of:

(i) forming a source and drain region by ion implantation;

(j) forming a fifth insulating layer and anisotropically etching the fifth insulating layer for forming a contact hole; and

(k) filling the contact hole with a third conductive layer, and patterning the third conductive layer into wiring.

9. The method according to claim 8, wherein in step (c), a thickness of the second insulating layer is thicker than a half length of the distance between the preliminary floating gate electrodes.

10. The method according to claim 8, in step (j), the fifth insulating layer is deposited with a thickness which is greater than a half length of the second distance between the gate electrodes and less than a half length of the first distance between the gate electrodes.

11. The method according to claim 8, wherein the etching process in step (j) includes steps of forming a photoresist mask which covers a peripheral circuit portion except for the contact hole and does not cover the cell forming area, etching the fifth insulating layer until a portion of the fifth insulating layer on a horizontal surface is removed so that a portion of the fifth insulating layer remains attached on a side wall of the gate patterns.

12. The method according to claim 7, wherein in step (b), the ion implanting is performed with a photoresist mask which covers a peripheral circuit portion.

13. The method according to claim 7, wherein the substrate has an isolation region therein.

14. The method according to claim 7, wherein step (h) uses the gate electrode as a mask.

15. A method for forming of a semiconductor device including a transistor having a floating gate, comprising the steps of:

(a) after forming a isolation region in the semiconductor substrate, forming a first insulating layer and a first conductive layer on the resulting surface of the substrate;

(b) forming preliminary floating gate electrodes by patterning the first conductive layer on a cell forming area, and implanting ions on the cell forming area;

(c) forming a second insulating layer on the resulting surface formed after step (b) and etching the second insulating layer back so that it remains on the side walls of the preliminary floating gate electrodes, thus filling the distance between the preliminary floating gate electrodes;

(d) forming a third insulating layer on the resulting surface formed after step (c), forming a second conductive layer on the third insulating layer, and forming a fourth insulating layer on the second conductive layer;

(e) forming gate electrode patterns by patterning the fourth insulating layer and the second conductive layer, wherein the gate electrode patterns are arranged in such a layout that a wide distance between the gate patterns is arranged in a portion to be a contact hole, and a narrow distance between the gate patterns is arranged in another portion;

(f) forming a floating gate electrode by patterning the third insulating layer and the second conductive layer using the gate electrode as mask, and forming a source and drain region by ion implantation;

(g) forming a fifth insulating layer and etching the fifth insulating layer back anisotropically, thus forming a contact hole; and

(h) filling the cantact hole with a third conductive layer, and patterning the third conductive layer into wiring.

16. The method according to claim 15, in step (c), the thickness of the second insulating layer is to be thicker than a half length of the distance between the preliminary floating gate electrodes.

17. The method according to claim 15, in step (g), the fifth insulating layer is deposited with a thickness which is thicker than a half length of the narrow distance between the gate electrodes and thinner than a half length of the wide distance between the gate electrodes.

18. The method according to claim 15, wherein the etching process of step (g) includes steps for forming a photoresist mask which covers a peripheral circuit portion except for the contact hole and does not cover the cell forming area, etching the fifth insulating layer until a portion of the fifth insulating layer on a horizontal surface is removed, thus leaving a portion of the fifth insulating layer on side walls of the gate patterns.

19. The method according to claim 15, wherein the ion implanting of step (b) is performed with a photoresist mask which covers a peripheral circuit portion.

20. The method according to claim 15, wherein the first, second, third, fourth and fifth insulating layers are formed of silicon oxide or silicon nitride, and the first, second, and third conductive layers are formed of polysilicon.