Flash memory cell and method of making the same

• US 5,702,965 A
• Filed: 06/19/1996
• Issued: 12/30/1997
• Est. Priority Date: 06/24/1995
• Status: Expired due to Term

• Current Assignee: SK Hynix Inc.
• Original Assignee: Hyundai Electronics Industries Co. Ltd. (SK Hynix Inc.)
• Inventors: Kim, Jeoung Woo
• Primary Examiner(s): DUTTON, BRIAN KEITH
• Application Number:
  US08/666,013
• Time in Patent Office: 559 Days
• Field of Search: 437/40 GS, 437/41 GS, 437/43, 437/48, 437/49, 437/40 AS, 437/41 AS, 437/52, 437/241, 437/40 SW, 437/41 SW, 257/314, 257/315, 257/316, 257/317, 257/318, 257/319, 257/320, 257/321, 257/322, 257/323, 365/185.01, 365/185.1, 365/185.26
• US Class Current: 438/261
• CPC Class Codes: H01L 29/42324 Gate electrodes for transistors with a floating gate
• CPC Class Codes: H01L 29/66825 with a floating gate H01L29/6684 takes precedence

Abstract

A highly efficient split-gate type flash memory cell with an insulation spacer of an ONO or ON structure formed at the side walls of the floating gate according to the present invention can improve program and erasure capabilities of the cell by preventing reduction of the coupling ratio and leakage of electrons through the floating gate and the control gate.

Claims

1. A method of making a flash memory cell in a semiconductor device, comprising:

sequentially forming a tunnel oxide film, a first polysilicon layer and an oxide film on a silicon substrate;

patterning said oxide film and said first polysilicon layer to form a floating gate on said substrate;

forming source and drain regions in said silicon substrate;

forming an insulating film on said tunnel oxide film, said first polysilicon layer and said oxide film after forming said source and drain regions, and forming an insulating film spacer at side walls of said oxide film and floating gate through an isotropic etching process, said insulating film having an ONO structure in which an underlying oxide film, a nitride film and an upper oxide film are sequentially stacked;

removing a portion of said oxide film remaining on said floating gate and performing a thermal oxidation process so as to form a select-gate oxide film on the exposed silicon substrate and a dielectric film on said floating gate;

forming a second polysilicon layer on said select-gate oxide film, said insulating film spacer and said dielectric film; and

patterning said second polysilicon layer to form a control gate.

2. The method of claim 1, wherein said underlying oxide film is a CVD oxide film.

3. The method of claim 1, wherein said underlying oxide film is a thermal oxide film.

4. A method of making a flash memory cell in a semiconductor device, comprising:

sequentially forming a tunnel oxide film and a first polysilicon layer on a silicon substrate;

patterning said first polysilicon layer to form a floating gate;

forming source and drain regions in said silicon substrate;

forming an insulating film on said tunnel oxide film and said first polysilicon layer after forming said source and drain regions, and forming an insulating film spacer at side walls of said floating gate through an isotropic etching process, said insulating film having an ONO structure in which an underlying oxide film, a nitride film and an upper oxide film are sequentially stacked;

performing a thermal oxidation process so as to form a select-gate oxide film on the exposed silicon substrate and a dielectric film on said floating gate;

forming a second polysilicon layer on said select-gate oxide film, said insulating film spacer and said dielectric film; and

patterning the second polysilicon layer to form a control gate.

5. The method of claim 4, wherein said underlying oxide film is a CVD oxide film.

6. The method of claim 4, wherein said underlying oxide film is a thermal oxide film.

7. A method of making a flash memory cell in a semiconductor device, comprising:

sequentially forming a tunnel oxide film, a first polysilicon layer and an oxide film on a silicon substrate;

patterning said oxide film and said first polysilicon layer to form a floating gate;

forming source and drain regions in said silicon substrate;

forming an insulating film on said tunnel oxide film, said first polysilicon layer and said oxide film after forming said source and drain regions, and forming an insulating film spacer at side walls of said oxide film and floating gate through an isotropic etching process, said insulating film having an ON structure in which an oxide film and a nitride film are sequentially stacked with respect to each other;

removing a portion of said oxide film remaining on said floating gate and performing a thermal oxidation process so as to form a select-gate oxide film on the exposed silicon substrate and a dielectric film on said floating gate;

forming a second polysilicon layer on said select-gate oxide film, said insulating film spacer and said dielectric film; and

patterning said second polysilicon layer to form a control gate.

8. The method of claim 7, wherein said oxide film is a CVD oxide film.

9. The method of claim 7, wherein said oxide film is a thermal oxide film.

10. A method of making a flash memory cell in a semiconductor device, comprising:

sequentially forming a tunnel oxide film and a first polysilicon layer on a silicon substrate;

patterning said first polysilicon layer to form a floating gate;

forming source and drain regions in said silicon substrate;

forming an insulating film on the said tunnel oxide film and said first polysilicon layer after forming said source and drain regions, and forming an insulating film spacer at side walls of said floating gate through an isotropic etching process, said insulating film having an ON structure in which an oxide film and a nitride film are sequentially stacked with respect to each other;

removing a portion of said oxide film remaining on said floating gate and performing a thermal oxidation process so as to form a select-gate oxide film on the exposed silicon substrate and a dielectric film on said floating gate;

forming a second polysilicon layer on said select-gate oxide film, and said insulating film spacer and said dielectric film; and

pattering said second polysilicon layer to form a control gate.

11. The method of claim 10, wherein said oxide film is a CVD oxide film.

12. The method of claim 10, wherein said oxide film is a thermal oxide film.