Current mirror circuit

• US 5,703,478 A
• Filed: 04/05/1996
• Issued: 12/30/1997
• Est. Priority Date: 04/05/1996
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Main, William Eric
• Primary Examiner(s): Wong, Peter S.
• Assistant Examiner(s): Patel, Rajnikant B.
• Application Number:
  US08/628,307
• Time in Patent Office: 634 Days
• Field of Search: 323/315, 323/313, 323/312, 323/316, 323/314, 327/538
• US Class Current: 323/315
• CPC Class Codes: G05F 3/265 using bipolar transistors only

Abstract

A current mirror circuit (31) that includes an active loop which operates transistors of different conductivity type at equal base-emitter junction voltages to minimize error. A first resistor (38) couples to a base of a first transistor (32) of a first conductivity type in a voltage follower configuration. A reference current is coupled to the first resistor (38). The voltage across the first resistor (38) and base-emitter junction of the first transistor (32) is mirrored across the base-emitter junction of a second transistor (34) of a second conductivity type and a second resistor (39). A third transistor (35) of the second conductivity type in a diode configuration is coupled to receive current from the second transistor (34). The voltage across the third transistor (35) biases a fourth transistor (33) of a first conductivity type. The current from the fourth transistor (33) is provided to the first transistor such that the first and second transistors (32,34) operate at equal base-emitter voltages.

Claims

1. A current mirror having an input for receiving a reference current and an output for providing an output current, the current mirror comprising:

a first resistor having a first terminal coupled to a first power supply terminal and a second terminal coupled to the input of the current mirror;

a first transistor of a first conductivity type having a first electrode coupled to said first power supply terminal, a control electrode coupled to the input of the current mirror, and a second electrode;

a second transistor of a second conductivity type having a first electrode, a control electrode coupled to said second electrode of said first transistor, and a second electrode;

a second resistor having a first terminal coupled to said second electrode of said second transistor and a second terminal coupled to said first power supply terminal;

a third transistor of said first conductivity type having a first electrode coupled to said second electrode of said first transistor, a control electrode coupled to said first electrode of said second transistor, and a second electrode coupled to a second power supply terminal; and

a fourth transistor of said second conductivity type having a first electrode coupled to said second power supply terminal, a control electrode coupled to said second power supply terminal, and a second electrode coupled to said first electrode of said second transistor.

2. The current mirror as recited in claim 1 wherein said second and fourth transistors have equal size.

3. The current mirror as recited in claim 2 wherein said first and third transistor have equal size.

4. The current mirror as recited in claim 3 wherein said first and second transistors have equal base-emitter junction voltages and wherein a current conducted by said second transistor corresponds to a ratio of a resistance of said second resistor to a resistance of said first resistor.

5. The current mirror as recited in claim 4 further including:

a fifth transistor of said second conductivity type having a first electrode coupled to the output of the current mirror, a control electrode coupled to said second electrode of said first transistor, and a second electrode; and

a third resistor having a first terminal coupled to said second electrode of said first transistor and a second terminal coupled to said first power supply terminal.

6. The current mirror as recited in claim 5 wherein a ratio of a conductive area of said fifth transistor to a conductive area of said second transistor equals a ratio of said resistance of said second resistor to a resistance of said third resistor.

7. The current mirror as recited in claim 3 wherein a conductive area of said first transistor is larger than a conductive area of said third transistor to insure an active loop comprising said first, second, third, and fourth transistors shuts down when the reference current is not provided to the current mirror.

8. The current mirror as recited in claim 7 further including a current source between the input of the current mirror and said second power supply terminal for increasing a voltage across said first resistor to compensate for a base-emitter junction voltage of said first transistor.

9. The current mirror as recited in claim 7 further including:

a resistor coupled between said control electrode of said fourth transistor and said second power supply terminal; and

a current source coupled between said first power supply terminal and said control electrode of said fourth transistor.

10. The current mirror as recited in claim 7 further including a resistor coupled between said control electrode of said third transistor and said second electrode of said fourth transistor.

11. The current mirror as recited in claim 10 further including a current source coupled between said first power supply terminal and said control electrode of said third transistor to start up the current mirror.

12. A method of increasing accuracy of a current mirror wherein the current mirror comprises transistors of different conductivity type, the method including a step of operating the transistors of different conductivity type having identical base-emitter junction voltages to minimize current mirror error.

13. The method as recited in claim 12 further including the steps of:

providing a current from a first transistor of a first conductivity type to a second transistor of said first conductivity type; and

generating a reference voltage corresponding to a base-emitter junction voltage of said second transistor wherein said second transistor is biased with said current from said first transistor.

14. The method as recited in claim 13 further including a step of biasing a base-emitter junction of a third transistor of a second conductivity type with said reference voltage.

15. The method as recited in claim 14 further including a step of providing a current from said third transistor to bias a fourth transistor of said second conductivity type.

16. The method as recited in claim 14 further including the steps of:

matching a conductive area of said first and second transistors; and

matching a conductive area of said third and fourth transistors wherein a base-emitter voltage of said first, second, third, and fourth transistors are equal.

17. A current mirror having an input for receiving a reference current and an output for providing an output current, the current mirror comprising:

a first resistor having a first terminal coupled to a first power supply terminal and a second terminal coupled to the input of the current mirror;

a first transistor of a first conductivity type having a first electrode coupled to said first power supply terminal, a control electrode coupled to the input of the current mirror, and a second electrode;

a second transistor of a second conductivity type having a first electrode, a control electrode coupled to said second electrode of said first transistor, and a second electrode;

second resistor having a first terminal coupled to said second electrode of said second transistor and a second terminal coupled to said first power supply terminal;

a third transistor of said first conductivity type having a first electrode coupled to said second electrode of said first transistor, a control electrode coupled to said first electrode of said second transistor, and a second electrode coupled to a second power supply terminal;

a fourth transistor of said second conductivity type having a first electrode coupled to said second power supply terminal, a control electrode coupled to said second power supply terminal, and a second electrode coupled to said first electrode of said second transistor;

a fifth transistor of said second conductivity type having a first electrode coupled to the output of the current mirror, a control electrode coupled to said second electrode of said first transistor, and a second electrode; and

a third resistor having a first terminal coupled to said second electrode of said first transistor and a second terminal coupled to said first power supply terminal.

18. A current mirror having an input for receiving a reference current and an output for providing an output current, the current mirror comprising:

a first resistor having a first terminal coupled to a first power supply terminal and a second terminal coupled to the input of the current mirror;

a first transistor of a first conductivity type having a first electrode coupled to said first power supply terminal, a control electrode coupled to the input of the current mirror, and a second electrode;

a second transistor of a second conductivity type having a first electrode, a control electrode coupled to said second electrode of said first transistor, and a second electrode;

a second resistor having a first terminal coupled to said second electrode of said second transistor and a second terminal coupled to said first power supply terminal;

a third transistor of said first conductivity type having a first electrode coupled to said second electrode of said first transistor, a control electrode coupled to said first electrode of said second transistor, and a second electrode coupled to a second power supply terminal; and

a fourth transistor of said second conductivity type having a first electrode coupled to the output of the current mirror, a control electrode coupled to said second electrode of said third transistor, and a second electrode coupled to said first electrode of said second transistor.

19. The current mirror as recited in claim 18 further including a level shift circuit coupled between said second electrode of said third transistor and said second power supply terminal.