Analog data acquisition system

• US 5,703,584 A
• Filed: 08/22/1994
• Issued: 12/30/1997
• Est. Priority Date: 08/22/1994
• Status: Expired due to Term

• Current Assignee: STMicroelectronics NV
• Original Assignee: Adaptec Incorporated (Steel Partners Holdings LP)
• Inventors: Hill, John P.
• Primary Examiner(s): Young, Brian K.
• Application Number:
  US08/293,973
• Time in Patent Office: 1,226 Days
• Field of Search: 341/141, 341/155
• US Class Current: 341/141
• CPC Class Codes: G11B 20/10037 A/D conversion, D/A conversion, sampling, slicing and digital quantisation or adjusting parameters thereof
• CPC Class Codes: G11B 5/59611 Detection or processing of peak/envelop signals

Abstract

An analog data acquisition system in an integrated circuit automatically processes and stores analog data without sequencing support from a processor. The analog data acquisition system converts each analog input signal into digital data. The digital data are stored in registers in the integrated circuit that are directly readable by a digital signal processor without data moves and are directly usable by the digital signal processor without further processing or conversion. Consequently, the analog data acquisition system minimizes the use of both the digital signal processor and the digital signal processor program memory and leaves capacity, i.e., both processing time and instruction memory locations, for use in other activities. The analog data acquisition system includes an analog input multiplexer and an analog-to-digital (A/D) converter that has an input line that is connected to the analog input multiplexer output line. An acquisition sequencer provides signals to the analog input multiplexer so that a signal on one of the plurality of input lines to the analog input multiplexer is applied to the A/D converter.

Claims

1. An analog data acquisition system comprising:

an analog input multiplexer having a plurality of input lines, an output line and a plurality of signal select lines;

an analog-to-digital (A/D) converter having an input line, a digital output bus, and a plurality of control lines;

wherein

said input line of said A/D converter is connected to said analog input multiplexer output line; and

an acquisition sequencer coupled to said plurality of signal select lines and to said plurality of control lines;

wherein said acquisition sequencer comprises;

a state machine connected to said plurality of control lines of said A/D converter wherein said state machine generates said signals over said plurality of control lines so that each signal on said A/D converter input line is converted to a digital signal; and

further wherein

said acquisition sequencer provides signals over said plurality of signal select lines so that a signal on one of said plurality of input lines to said analog input multiplexer is applied to said A/D converter; and

said acquisition sequencer provides signals over said plurality of control lines so that each signal on said A/D converter input line is converted to a digital signal.

2. The analog data acquisition system of claim 1 further comprising a memory connected to said digital output bus of said A/D converter wherein a portion of said memory is within a memory space of a processor so that data in said memory can be read directly by said processor without a data move.

3. The analog data acquisition system of claim 2 wherein said memory comprises a plurality of registers.

4. The analog data acquisition system of claim 3 wherein said acquisition sequencer further comprises:

a counter circuit coupled to said plurality of registers;

wherein

said counter circuit generates a signal to select one of said plurality of registers into which said digital data on said digital bus of said A/D converter are loaded.

5. The analog data acquisition system of claim 3 further comprising a register having a plurality of bits connected to said acquisition sequencer wherein said plurality of bits select one of said plurality of registers into which said digital data on said digital bus of said A/D converter are loaded.

6. The analog data acquisition system of claim 1 wherein said acquisition sequencer further comprises:

a counter circuit coupled to said plurality of signal select lines of said analog input multiplexer and coupled to a conversion in progress signal line of said state machine;

wherein, in response to an active signal on said conversion in progress signal line, said counter circuit generates signals on said plurality of signal select lines so that a selected one of signals on said analog input multiplexer input lines are passed through said analog input multiplexer to said analog input multiplexer output line.

7. The analog data acquisition system of claim 6 wherein said state machine further comprises an increment in counter line connected to said counter circuit wherein said state machine generates an active signal on said increment in counter line to change the value of said counter circuit.

8. The analog data acquisition system of claim 1 further comprising a register having a plurality of bits connected to said acquisition sequencer wherein said plurality of bits generates signals on said plurality of signal select lines so that a selected one of signals on said analog input multiplexer input lines are passed through said analog input multiplexer to said analog input multiplexer output line.

9. The analog data acquisition system of claim 1 wherein said acquisition sequencer further comprises:

a counter circuit coupled to said plurality of signal select lines of said analog input multiplexer;

wherein said counter circuit generates signals on said plurality of signal select lines so that a selected one of signals on said analog input multiplexer input lines are passed through said analog input multiplexer to said analog input multiplexer output line.

10. The analog data acquisition system of claim 1 further comprising a multiplicity of configurable buffers wherein each configurable buffer has an output terminal that is selectively connectable to and disconnectable from one of said plurality of input lines of said analog multiplexer

wherein upon connecting said configurable buffer to said one of plurality of input lines of said analog multiplexer, said analog multiplexer receives a buffered input signal;

and

upon disconnecting said configurable buffer from said one of plurality of input lines of said analog multiplexer, said analog multiplexer receives an unbuffered input signal.

11. The analog data acquisition system of claim 1 wherein a first set of said plurality of input lines of said analog input multiplexer are servo position burst input lines.

12. The analog data acquisition system of claim 11 further comprising an operational amplifier having an output terminal connected to one of said plurality of input lines of said analog input multiplexer.

13. The analog data acquisition system of claim 1 further comprising an operational amplifier having an output terminal connected to one of said plurality of input lines of said analog input multiplexer.

14. The analog data acquisition system of claim 1 further comprising a channel input signal select multiplexer having an output line connected of one of said plurality of input lines of said analog input multiplexer and a plurality of input lines wherein in response to an input select signal, said channel input signal select multiplexer passes therethrough a signal on one of said plurality of channel input signal select multiplexer input lines to said output line.

15. The analog data acquisition system of claim 1 wherein said A/D converter further comprises a plurality of reference voltage input lines.

16. The analog data acquisition system of claim 15 further comprising;

an A/D reference select and buffers circuit connected to said plurality of reference voltage input lines and having a plurality of input lines.

17. The analog data acquisition system of claim 16 wherein a first set of said plurality of input lines of said A/D reference select and buffers circuit are connected to input pins of an integrated circuit containing said analog data acquisition system.

18. The analog data acquisition system of claim 1 further comprising an acquisition command register coupled to said acquisition sequencer and having a plurality of bits wherein for one configuration of said plurality of bits said acquisition sequencer operates in a pipelined mode.

19. The analog data acquisition system of claim 1 further comprising an acquisition status register coupled to said acquisition sequencer.

20. In an integrated circuit having a plurality of pins, an analog data acquisition system comprising:

a first plurality of inputs lines;

an analog input multiplexer connected to said first plurality of input lines and having a plurality of channel select lines and an output line;

an A/D reference select and buffers circuit having;

a first plurality of input lines connected to a plurality of said pins;

a second plurality of input lines connected to a reference voltage source within said integrated circuit; and

a plurality of reference voltage output lines;

an analog-to-digital (A/D) converter having;

an input terminal connected to said output line of said analog input multiplexer;

a plurality of reference voltage input terminals connected to said plurality of reference voltage output lines;

a plurality of control input lines; and

a digital output bus interface;

an acquisition sequencer circuit connected to said plurality of channel select lines, to said plurality of control lines and having a plurality of output load lines; and

a memory coupled to said digital output bus interface of said A/D converter and to said plurality of output load lines wherein in a first mode of operation said analog data acquisition system operates in a pipeline mode and in a second mode of operation said analog data acquisition system operates in a single channel mode.

21. An analog data acquisition system comprising:

an analog input multiplexer having a plurality of input lines, an output line and a plurality of signal select lines wherein a first set of said plurality of input lines of said analog input multiplexer are servo position burst input lines;

an analog-to-digital (A/D) converter having an input line, a digital output bus, and a plurality of control lines;

wherein

said input line of said A/D converter is connected to said analog input multiplexer output line; and

an acquisition sequencer coupled to said plurality of signal select lines and to said plurality of control lines;

wherein

said acquisition sequencer provides signals over said plurality of signal select lines so that a signal on one of said plurality of input lines to said analog input multiplexer is applied to said A/D converter; and

said acquisition sequencer provides signals over said plurality of control lines so that each signal on said A/D converter input line is converted to a digital signal.

22. The analog data acquisition system of claim 21 further comprising a memory connected to said digital output bus of said A/D converter wherein a portion of said memory is within a memory space of a processor so that data in said memory can be read directly by said processor without a data move.

23. The analog data acquisition system of claim 22 wherein said memory comprises a plurality of registers.

24. The analog data acquisition system of claim 23 wherein said acquisition sequencer further comprises:

a counter circuit coupled to said plurality of registers;

wherein

said counter circuit generates a signal to select one of said plurality of registers into which said digital data on said digital bus of said A/D converter are loaded.

25. The analog data acquisition system of claim 23 further comprising a register having a plurality of bits connected to said acquisition sequencer wherein said plurality of bits select one of said plurality of registers into which said digital data on said digital bus of said A/D converter are loaded.

26. The analog data acquisition system of claim 21 wherein said acquisition sequencer further comprises:

a state machine connected to said plurality of control lines of said A/D converter wherein said state machine generates said signals over said plurality of control lines so that each signal on said A/D converter input line is converted to a digital signal.

27. The analog data acquisition system of claim 26 wherein said acquisition sequencer further comprises:

a counter circuit coupled to said plurality of signal select lines of said analog input multiplexer and coupled to a conversion in progress signal line of said state machine;

wherein, in response to an active signal on said conversion in progress signal line, said counter circuit generates signals on said plurality of signal select lines so that a selected one of signals on said analog input multiplexer input lines are passed through said analog input multiplexer to said analog input multiplexer output line.

28. The analog data acquisition system of claim 27 wherein said state machine further comprises an increment in counter line connected to said counter circuit wherein said state machine generates an active signal on said increment in counter line to change the value of said counter circuit.

29. The analog data acquisition system of claim 21 wherein said analog data acquisition further comprising a register having a plurality of bits connected to said acquisition sequencer wherein said plurality of bits generates signals on said plurality of signal select lines so that a selected one of signals on said analog input multiplexer input lines are passed through said analog input multiplexer to said analog input multiplexer output line.

30. The analog data acquisition system of claim 21 wherein said acquisition sequencer further comprises:

a counter circuit coupled to said plurality of signal select lines of said analog input multiplexer;

wherein said counter circuit generates signals on said plurality of signal select lines so that a selected one of signals on said analog input multiplexer input lines are passed through said analog input multiplexer to said analog input multiplexer output line.

31. The analog data acquisition system of claim 21 further comprising a multiplicity of configurable buffers wherein each configurable buffer has an output terminal that is selectively connectable to and disconnectable from one of said plurality of input lines of said analog multiplexer

wherein upon connecting said configurable buffer to said one of plurality of input lines of said analog multiplexer, said analog multiplexer receives a buffered input signal;

and

upon disconnecting said configurable buffer from said one of plurality of input lines of said analog multiplexer, said analog multiplexer receives an unbuffered input signal.

32. The analog data acquisition system of claim 21 further comprising an operational amplifier having an output terminal connected to one of said plurality of input lines of said analog input multiplexer.

33. The analog data acquisition system of claim 21 further comprising an operational amplifier having an output terminal connected to one of said plurality of input lines of said analog input multiplexer.

34. The analog data acquisition system of claim 21 further comprising a channel input signal select multiplexer having an output line connected of one of said plurality of input lines of said analog input multiplexer and a plurality of input lines wherein in response to an input select signal, said channel input signal select multiplexer passes therethrough a signal on one of said plurality of channel input signal select multiplexer input lines to said output line.

35. The analog data acquisition system of claim 21 wherein said A/D converter further comprises a plurality of reference voltage input lines.

36. The analog data acquisition system of claim 35 further comprising;

an A/D reference select and buffers circuit connected to said plurality of reference voltage input lines and having a plurality of input lines.

37. The analog data acquisition system of claim 36 wherein a first set of said plurality of input lines of said A/D reference select and buffers circuit are connected to input pins of an integrated circuit containing said analog data acquisition system.

38. The analog data acquisition system of claim 21 further comprising an acquisition command register coupled to said acquisition sequencer and having a plurality of bits wherein for one configuration of said plurality of bits said acquisition sequencer operates in a pipelined mode.

39. The analog data acquisition system of claim 21 further comprising an acquisition status register coupled to said acquisition sequencer.