Multichip semiconductor structures with interchip electrostatic discharge protection, and fabrication methods therefore

• US 5,703,747 A
• Filed: 02/22/1995
• Issued: 12/30/1997
• Est. Priority Date: 02/22/1995
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Voldman, Steven Howard, Bakeman, Paul Evans Jr.
• Primary Examiner(s): Gaffin, Jeffrey A.
• Assistant Examiner(s): Medley, Sally C.
• Application Number:
  US08/392,461
• Time in Patent Office: 1,042 Days
• Field of Search: 361/56, 361/91, 361/111, 361/212, 361/220, 361/717, 361/735, 361/799
• US Class Current: 361/111
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 23/60 Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Interchip and intrachip electrical discharge suppression connections or networks are disclosed for three-dimensional multichip semiconductor structures. The interchip suppression networks electrically intercouple the power planes of the semiconductor device chips in the structure. This, in combination with conventional intrachip suppression networks present on the external connects or input/output pins of the individual chips in the structure, provides complete power plane-to-power plane, external connect-to-power plane and external connect-to-external connect protection against electrical discharge events, such as an electrostatic discharge occurring during handling and testing of the structure. The interchip electrical discharge suppression networks can be placed on an end layer or end semiconductor chip of the three-dimensional multichip semiconductor structure and connect to individual chips in the structure via an edge surface metallization. Techniques for suppressing electrical discharges occurring during the fabrication of three-dimensional multichip semiconductor structure are also disclosed.

Claims

1. A multichip semiconductor device structure comprising:

a first chip having a first planar main surface;

a second semiconductor device chip having a second planar main surface, said first chip and said second semiconductor device chip being stacked together such that said first planar surface of said first chip is parallel to said second planar main surface of said second semiconductor device chip; and

interchip electrical discharge suppression means electrically coupling said first chip and said second semiconductor device chip for suppressing an electrical discharge occurring therebetween.

2. The structure of claim 1, wherein said first chip comprises a first semiconductor device chip, said first semiconductor device chip including a first power plane and said second semiconductor device chip including a second power plane, and wherein said interchip electrical discharge suppression means electrically couples said first power plane and said second power plane.

3. The structure of claim 2, wherein said first power plane and said second power plane provide a first supply voltage to said first semiconductor device chip and to said second semiconductor device chip, respectively.

4. The structure of claim 3, wherein said first supply voltage comprises a ground voltage Vss, and wherein said interchip electrical discharge suppression means comprises means for electrically shorting said first power plane to said second power plane.

5. The structure of claim 2, wherein said first power plane provides a first supply voltage to said first semiconductor device chip and said second power plane provides a second supply voltage to said second semiconductor device chip, said first supply voltage being different from said second supply voltage.

6. The structure of claim 5, wherein said first semiconductor device chip includes a third power plane and said second semiconductor device chip includes a fourth power plane, said third power plane providing said second supply voltage to said first semiconductor device chip and said fourth power plane providing said first supply voltage to said second semiconductor device chip, and wherein said interchip electrical discharge suppression means also electrically couples said third power plane and said fourth power plane.

7. The structure of claim 6, wherein said interchip electrical discharge suppression means also electrically couples said first power plane to said fourth power plane, and electrically couples said third power plane to said second power plane.

8. The structure of claim 7, wherein said first semiconductor device chip includes at least one external connect and said second semiconductor device chip includes at least one external connect, and wherein said first semiconductor device chip and said second semiconductor device chip each further comprises an intrachip electrical discharge suppression network, the intrachip electrical discharge suppression network of said first semiconductor device chip electrically coupling its at least one external connect to said first power plane and to said third power plane, and the intrachip electrical discharge suppression network of said second semiconductor device chip electrically coupling its at least one external connect to said second power plane and to said fourth power plane, wherein said at least one external connect of said first semiconductor device chip is electrically coupled to said at least one external connect of said second semiconductor device chip via said intrachip electrical discharge suppression networks and said interchip electrical discharge suppression means for suppression of an electrical discharge occurring therebetween.

9. The structure of claim 1, further comprising a third semiconductor device chip, and wherein said interchip electrical discharge suppression means is disposed within said third semiconductor device chip.

10. The structure of claim 9, wherein said third semiconductor device chip has a third planar main surface and wherein said third semiconductor device chip is stacked together with said first chip and said second semiconductor device chip, with said third planar main surface being parallel to said first and second planar main surfaces, said third semiconductor device chip comprising an end semiconductor device chip in said multichip semiconductor device structure.

11. The structure of claim 10, wherein said end semiconductor device chip includes a plurality of different electrical discharge suppression networks, said interchip electrical discharge suppression means comprising one electrical discharge suppression network of said plurality of different electrical discharge suppression networks.

12. The structure of claim 11, wherein said interchip electrical discharge suppression means electrically connects to said first chip and to said second semiconductor device chip via metallization on an edge surface of said multichip semiconductor device structure.

13. The structure of claim 1, wherein said interchip electrical discharge suppression means is at least partially disposed within said second semiconductor device chip.

14. The structure of claim 1, wherein said interchip electrical discharge suppression means is bidirectional for suppression of a positive electrical discharge or a negative electrical discharge occurring between said first chip and said second semiconductor device chip.

15. A multichip semiconductor stack comprising:

a first semiconductor device chip having a first substrate, a first Vcc supply, a first Vss supply, and a first input/output connect, said first semiconductor device chip further including a first intrachip electrostatic discharge protection circuit electrically coupled between said first input/output connect and said first Vcc supply, and between said first input/output connect and said first Vss supply;

a second semiconductor device chip having a second substrate, a second Vcc supply, a second Vss supply, and a second input/output connect, said second semiconductor device chip further including a second intrachip electrostatic discharge protection circuit electrically coupled between said second input/output connect and said second Vcc supply, and between said second input/output connect and said second Vss supply; and

an interchip electrostatic discharge protection network interconnecting said first semiconductor device chip and said second semiconductor device chip such that

said first Vcc supply is electrically coupled to said second Vcc supply,

said first Vss supply is electrically coupled to said second Vss supply,

said first Vcc supply is electrically coupled to said second Vss supply, and

said first Vss supply is electrically coupled to said second Vcc supply.

16. The multichip semiconductor stack of claim 15, wherein said interchip electrostatic discharge protection network is disposed at least partially within said first semiconductor device chip.

17. The multichip semiconductor stack of claim 15, wherein said interchip electrostatic discharge protection network is disposed at least partially within an end layer of said semiconductor stack.

18. The multichip semiconductor stack of claim 17, wherein said end layer includes contact pads for external electrical connection to said multichip semiconductor stack.

19. A method for fabricating a semiconductor structure comprising:

(a) forming a multichip stack by stacking together a first semiconductor device chip having a first planar main surface and a second semiconductor device chip having a second planar main surface such that said first planar main surface is parallel to said second planar main surface;

(b) metallizing a first edge surface of said multichip stack such that a substrate of said first semiconductor device chip is electrically connected to a substrate of said second semiconductor device chip; and

(c) subsequent to said step (b), forming a metallization pattern on a second edge surface of said semiconductor structure, said metallization pattern including at least one external connect of said first semiconductor device chip and at least one external connect of said second semiconductor device chip.