Logarithm/inverse-logarithm converter utilizing second-order term and method of using same

• US 5,703,801 A
• Filed: 01/31/1995
• Issued: 12/30/1997
• Est. Priority Date: 01/31/1995
• Status: Expired due to Fees

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Wang, Shay-Ping Thomas, Pan, ShaoWei
• Primary Examiner(s): Elmore, Reba I.
• Assistant Examiner(s): MOISE, EMMANUEL LIONEL
• Application Number:
  US08/382,467
• Time in Patent Office: 1,064 Days
• Field of Search: 364/722, 364/748, 364/748.5, 364/715.03, 364/736, 341/75
• US Class Current: 708/517
• CPC Class Codes: G06F 1/0356 by using two or more smaller tables, e.g. addressed by parts of the argument
• CPC Class Codes: G06F 2101/10 Logarithmic or exponential functions
• CPC Class Codes: H03M 7/50 Conversion to or from non-linear codes, e.g. companding

Abstract

A converter which may be used for implementing either logarithmic or inverse-logarithmic functions is disclosed. The converter includes a memory, a multiplier, and two adders. The memory stores a plurality of parameters and second-order terms which are derived using a least squares method to estimate a logarithmic or inverse-logarithmic function over a domain of input values. A method of computing the parameters and second-order terms is also disclosed.

Claims

1. A logarithm converter, which comprises:

a memory for storing a plurality of parameters and a plurality of second-order terms, wherein the parameters are calculated using a least squares method to estimate a logarithmic function over a domain of input values, the memory providing as output ones of the parameters and a second-order term which correspond to an input value; and

arithmetic means, operatively coupled to the memory, for generating a log value by performing arithmetic operations on the input value, the ones of the parameters, and the second-order term.

2. The logarithm converter of claim 1, wherein the logarithmic function is estimated with a second-order polynomial.

3. The logarithm converter of claim 2, wherein the ones of the plurality of parameters include a zero-order parameter and a first-order parameter, and the arithmetic means includes:

a multiplier for multiplying the first-order parameter by the input value to produce a proportional term;

a first adder for summing the proportional term and the second-order term to produce a first sum; and

a second adder for summing the first sum and the zero-order parameter to produce the log value.

4. The logarithm converter of claim 2, wherein the ones of the plurality of parameters include a zero-order parameter and a first-order parameter, and the arithmetic means includes:

a multiplier for multiplying the first-order parameter by a bit slice of the input value to produce a proportional term;

a first adder for summing the proportional term and the second-order term to produce a first sum; and

a second adder for summing the first sum and the zero-order parameter to produce the log value.

5. The logarithm converter of claim 1, wherein the input value is a binary value having a plurality of bits used to retrieve from the memory the ones of the plurality of parameters and the second-order term.

6. The logarithm converter of claim 1, wherein the input value is a binary value having an upper portion and a lower portion, and the second-order term is retrievable from the memory using a first bit slice from the upper portion concatenated with a second bit slice from the lower portion.

7. A logarithm converter for generating a log value corresponding to an input value, the logarithm converter comprising:

a memory for storing a plurality of second-order terms and a plurality of parameter pairs, wherein each of the parameter pairs is calculated using a least squares method to estimate a logarithmic function over an interval of input values, the memory providing as output a parameter pair and a second-order term which correspond to the input value, wherein the parameter pair has a zero-order parameter and a first-order parameter;

a multiplier for multiplying the first-order parameter by a bit slice of the input value to produce a proportional term;

a first adder for summing the proportional term and the second-order term to produce a first sum; and

a second adder for summing the first sum and the zero-order parameter to produce the log value.

8. The logarithm converter of claim 7, wherein the input value is a binary value having a plurality of bits used to retrieve the parameter pair from the memory.

9. The logarithm converter of claim 7, wherein the input value is a binary value having an upper portion and a lower portion, and the second-order term is retrievable from the memory using a first bit slice from the upper portion concatenated with a second bit slice from the lower portion.

10. The logarithm converter of claim 7, wherein the logarithmic function is estimated with a second order polynomial.

11. A computing device, which comprises:

a processing unit for executing a computer operation which utilizes a log value;

a computer memory for storing a computer program which includes the computer operation;

a bus for connecting the processing unit and the computer memory; and

a logarithm converter which receives an input value and includes;

a memory for storing a plurality of parameters and a plurality of second-order terms, wherein the parameters are calculated using a least squares method to estimate a logarithmic function over a domain of input values, the memory providing as output ones of the parameters and a second-order term which correspond to the input value; and

arithmetic means, operatively coupled to the memory, for generating the log value by performing arithmetic operations on the input value, the ones of the parameters, and the second-order term.

12. The computing device of claim 11, wherein the logarithmic function is estimated with a second-order polynomial.

13. The computing device of claim 11, wherein the plurality of parameters include a zero-order parameter and a first-order parameter, and the arithmetic means includes:

a multiplier for multiplying the first-order parameter by a bit slice of the input value to produce a proportional term;

a first adder for summing the proportional term and the second-order term to produce a first sum; and

a second adder for summing the first sum and the zero-order parameter to produce the log value.

14. The computing device of claim 11, wherein the input value is a binary value having a plurality of bits used to retrieve from the memory the ones of the plurality of parameters.

15. The logarithm converter of claim 11, wherein the input value is a binary value having an upper portion and a lower portion, and the second-order term is retrievable from the memory using a first bit slice from the upper portion concatenated with a second bit slice from the lower portion.

16. An inverse-logarithm converter, which comprises:

a memory for storing a plurality of parameters and a plurality of second-order terms, wherein the parameters are calculated using a least squares method to estimate an inverse-logarithmic function over a domain of input values, the memory providing as output ones of the parameters and a second-order term which correspond to an input value; and

arithmetic means, operatively coupled to the memory, for generating an inverse-log value by performing arithmetic operations on the input value, the ones of the parameters, and the second-order term.

17. The inverse-logarithm converter of claim 16, wherein the inverse-logarithmic function is estimated with a second-order polynomial.

18. The inverse-logarithm converter of claim 17, wherein the ones of the plurality of parameters include a zero-order parameter and a first-order parameter, and the arithmetic means includes:

a multiplier for multiplying the first-order parameter by the input value to produce a proportional term;

a first adder for summing the proportional term and the second-order term to produce a first sum; and

a second adder for summing the first sum and the zero-order parameter to produce the inverse-log value.

19. The inverse-logarithm converter of claim 17, wherein the ones of the plurality of parameters include a zero-order parameter and a first-order parameter, and the arithmetic means includes:

a multiplier for multiplying the first-order parameter by a bit slice of the input value to produce a proportional term;

a first adder for summing the proportional term and the second-order term to produce a first sum; and

a second adder for summing the first sum and the zero-order parameter to produce the inverse-log value.

20. The inverse-logarithm converter of claim 16, wherein the input value is a binary value having a plurality of bits used to retrieve from the memory the ones of the plurality of parameters and the second-order term.

21. The inverse-logarithm converter of claim 16, wherein the input value is a binary value having an upper portion and a lower portion, and the second-order term is retrievable from the memory using a first bit slice from the upper portion concatenated with a second bit slice from the lower portion.

27. The computing device of claim 16, wherein the inverse-logarithmic function is estimated with a second-order polynomial.

28. The computing device of claim 27, wherein the plurality of parameters include a zero-order parameter and a first-order parameter, and the arithmetic means includes:

a multiplier for multiplying the first-order parameter by a bit slice of the input value to produce a proportional term;

a first adder for summing the proportional term and the second-order term to produce a first sum; and

a second adder for summing the first sum and the zero-order parameter to produce the inverse-log value.

22. An inverse-logarithm converter for generating an inverse-log value corresponding to an input value, the inverse-logarithm converter comprising:

a memory for storing a plurality of second-order terms and a plurality of parameter pairs, wherein each of the parameter pairs is calculated using a least squares method to estimate an inverse-logarithmic function over an interval of input values, the memory providing as output a parameter pair and a second-order term which correspond to the input value, wherein the parameter pair has a zero-order parameter and a first-order parameter;

a multiplier for multiplying the first-order parameter by a bit slice of the input value to produce a proportional term;

a first adder for summing the proportional term and the second-order term to produce a first sum; and

a second adder for summing the first sum and the zero-order parameter to produce the inverse-log value.

23. The inverse-logarithm converter of claim 22, wherein the input value is a binary value having a plurality of bits used to retrieve the parameter pair from the memory.

24. The inverse-logarithm converter of claim 22, wherein the input value is a binary value having an upper portion and a lower portion, and the second-order term is retrievable from the memory using a first bit slice from the upper portion concatenated with a second bit slice from the lower portion.

25. The inverse-logarithm converter of claim 22, wherein the inverse-logarithmic function is estimated with a second order polynomial.

26. A computing device, which comprises:

a processing unit for executing a computer operation which utilizes an inverse-log value;

a computer memory for storing a computer program which includes the computer operation;

a bus for connecting the processing unit and the computer memory; and

an inverse-logarithm converter which receives an input value and includes;

a memory for storing a plurality of parameters and a plurality of second-order terms, wherein the parameters are calculated using a least squares method to estimate an inverse-logarithmic function over a domain of input values, the memory providing as output ones of the parameters and a second-order term which correspond to the input value; and

arithmetic means, operatively coupled to the memory, for generating the inverse-log value by performing arithmetic operations on the input value, the ones of the parameters, and the second-order term.

29. The computing device of claim 26, wherein the input value is a binary value having a plurality of bits used to retrieve from the memory the ones of the plurality of parameters.

30. The inverse-logarithm converter of claim 26, wherein the input value is a binary value having an upper portion and a lower portion, and the second-order term is retrievable from the memory using a first bit slice from the upper portion concatenated with a second bit slice from the lower portion.