Efficient explicit data prefetching analysis and code generation in a low-level optimizer for inserting prefetch instructions into loops of applications

• US 5,704,053 A
• Filed: 05/18/1995
• Issued: 12/30/1997
• Est. Priority Date: 05/18/1995
• Status: Expired due to Term

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Hewlett-Packard Company (HP Inc.)
• Inventors: Santhanam, Vatsa
• Primary Examiner(s): Lee, Thomas C.
• Assistant Examiner(s): Ton, David
• Application Number:
  US08/443,653
• Time in Patent Office: 957 Days
• Field of Search: 395/425, 395/375, 395/700, 395/383, 395/705
• US Class Current: 717/158
• CPC Class Codes: G06F 8/4442 Reducing the number of cache misses; Data prefetching cache prefetching G06F12/0862
• CPC Class Codes: G06F 9/30047 Prefetch instructions; cache control instructions
• CPC Class Codes: G06F 9/383 Operand prefetching cache prefetching G06F12/0862

Abstract

A compiler that facilitates efficient insertion of explicit data prefetch instructions into loop structures within applications uses simple address expression analysis to determine data prefetching requirements. Analysis and explicit data cache prefetch instruction insertion are performed by the compiler in a machine-instruction level optimizer to provide access to more accurate expected loop iteration latency information. Such prefetch instruction insertion strategy tolerates worst-case alignment of user data structures relative to data cache lines. Execution profiles from previous runs of an application are exploited in the insertion of prefetch instructions into loops with internal control flow. Cache line reuse patterns across loop iterations are recognized to eliminate unnecessary prefetch instructions. The prefetch insertion algorithm is integrated with other low-level optimization phases, such as loop unrolling, register reassociation, and instruction scheduling. An alternative embodiment of the compiler limits the insertion of explicit prefetch instructions to those situations where the lower bound on the achievable loop iteration latency is unlikely to be increased as a result of the insertion.

Claims

1. A compiler, comprising:

means in a low level optimizer for analyzing and efficiently inserting explicit data prefetch instructions into loops of applications;

subscript expression analysis means for determining data prefetching requirements;

means for recognizing cache line reuse patterns across loop iterations to eliminate unnecessary prefetch instructions; and

means for limiting insertion of explicit prefetch instructions to situations where a lower bound on an achievable loop iteration latency is unlikely to be increased as a result of said prefetch instruction insertion.

2. The compiler of claim 1, wherein analysis and explicit data cache prefetch instruction insertion are performed by said compiler in a machine instruction level optimizer.

3. The compiler of claim 1, further comprising:

means for exploiting execution profiles from previous runs of an application during insertion of prefetch instructions into innermost loops with internal control flow.

4. The compiler of claim 1, wherein said prefetch insertion means is integrated with other low-level optimization phases.

5. The compiler of claim 4, said other low-level optimization phases comprising:

any of loop Unrolling, register reassociation, and instruction scheduling.

6. A method for mitigating or eliminating cache misses in a low level optimizer, comprising the steps of:

performing loop body analysis;

unrolling loops to reduce prefetch instruction overhead;

identifying uniformly generated equivalence classes of memory references in a code stream, where said equivalence classes represent disjoint sets of memory references occurring in a loop whose address expressions can be expressed as a linear function of the same basic loop induction variable and are known to differ only by a compile time constant, allowing the detection of group spatial and group temporal locality among said different memory references;

computing an effective memory stride for each of the equivalence classes;

determining the number of prefetch instructions needed for full cache miss coverage for each equivalence class, where the number of prefetch instructions that needs to be inserted is a function of the style of prefetching desired, including dumb prefetching that inserts an explicit prefetch instruction for each memory reference, baseline prefetching that inserts as many prefetch instructions as possible without affecting the resource minimum loop iteration latency, and selective prefetching that inserts as many prefetch instructions as are required to ensure full cache miss coverage, exploiting any group-spatial or group-temporal locality that may be apparent among memory references within a uniformly generated equivalence class; and

inserting prefetch instructions identified into said code stream.

7. The method of claim 6, further comprising the step of:

estimating a prefetch iteration distance for a loop as the ratio of average miss latency and average loop iteration latency, where the average loop iteration latency is derived from a resource-constrained lower bound on a cycle count based on machine resource usage.

8. The method of claim 6, further comprising the step of:

substituting a fixed constant value for unknown terms into the address expressions for memory references to run-time dimensioned arrays to facilitate partitioning of such references into disjoint equivalence classes.

9. The method of claim 6, further comprising the step of:

determining the number of prefetch instructions that are needed for each uniformly generated equivalence class for a selective prefetching strategy.

10. The method of claim 9, further comprising the step of:

sorting the address expressions for memory references belonging to an equivalence class based on their relative constant differences.

11. The method of claim 9, further comprising the step of:

determining an effective memory stride for the memory references associated with each equivalence class and classifying the effective memory stride as being either large or small based on whether it is greater than the cache line size.

12. The method of claim 9, further comprising the step of:

determining prefetch memory distance for the memory references associated with each equivalence class as the product of effective memory stride and prefetch iteration distance for the loop.

13. The method of claim 9, further comprising the step of:

removing memory references within a small-stride equivalence class that trail other memory references within said equivalence class by less than the prefetch memory distance, wherein memory references that remain are cluster leaders.

14. The method of claim 9, further comprising the step of:

grouping the memory references belonging to a large-stride equivalence class that are sorted by their constant address expression differences into clusters each of which has a distinct memory reference designated as the cluster leader and zero or more memory references designated as cluster trailers.

15. The method of claim 9, further comprising the step of:

merging clusters represented by their leaders to profitably exploit group temporal locality in a pairwise fashion.

16. The method of claim 6, further comprising the steps of:

deciding which equivalence classes to insert prefetch instructions for an under the baseline prefetching strategy by first sorting uniformly generated equivalence classes based on a prefetch cost/expected benefit criteria, and only committing to insert prefetch instructions for those equivalence classes with the best cost/expected benefit ratio, without causing resource-based minimum loop iteration latency to be exceeded.

17. The method of claim 6, further comprising the steps of:

running through clusters in each equivalence class;

generating explicit prefetch instructions for each cluster; and

inserting said prefetch instructions into the code stream.